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Texas Rangers' Corey Seager finished the season with a bone spur in his elbow
Chris Young, the team's president of baseball operations, said Monday that Seager had the issue for a couple of months.
iPhone Duo Reportedly Facing Production Problems Ahead of Launch
The iPhone Duo is reportedly facing production difficulties ahead of its October launch, with early output expected to be limited. A person said to be close to Foxconn's supply chain told China's Jiemian News that final assembly yields for Apple's first foldable iPhone were only slightly above 60% as of September 17. The source said that, under Apple's current quality standards, it could take another six months to a year for the assembly line to reach a mature yield.
Authorities announce ‘new possible ransom note’ in search for Savannah Guthrie’s mom Nancy Guthrie
The Pima County Sheriff’s Department confirmed an investigation into the potential ransom note, nearly eight months after the “Today” anchor’s mother disappeared.
Wish every NBA player would go play six months in …
Wish every NBA player would go play six months in …
Commentary: Never heard 'Choosin' Texas'? Consider that a wake-up call
Music fans and journalists who spent the last few months looking for the song of the summer faced a plot twist fit for Hollywood: The winner was a single released
Liverpool Midfielder given ultimatum amid contract standoff
Julian Ward is taking over as Liverpool’s sporting director in the middle of an important transition period. The last 18 months have seen the Reds be very active in the transfer market, meaning lot...
Galaxy S27 Ultra camera could solve two major issues seen on Samsung phones
The launch of the Galaxy S27 series is still four months away, but most details about the lineup's phones have already leaked. While the Galaxy S27 Ultra's basi
The Russian Prison That Evan Gershkovich Carried Home
In an interview, Mr. Gershkovich, a Wall Street Journal reporter who was imprisoned in Russia for 16 months, described his ordeal and the moment that nearly broke him.
Nancy Guthrie investigators reviewing possible new ransom note
Nearly eight months into Nancy Guthrie's alleged kidnapping case, law enforcement is assessing the credibility of an alleged new ransom note.
Despite Setbacks, NASA Gives Boeing’s Starliner Spacecraft a Boost
A previous mission left two astronauts stuck in space for months. Still, the space agency is investing $359 million to keep the craft flying.
NY1 Exclusive: Brooklyn Dem chair backs out of party race
After months of infighting, the chair of the Brooklyn Democratic Party, Rodneyse Bichotte Hermelyn, told NY1 she will not be seeking another term.
Pope Leo defends entering political fray on France end-of-life law
Pope Leo on Monday defended his decision to vocally oppose assisted dying initiatives while in France, acknowledging he may have entered the political fray two months after the country approved such a measure, but wanted to share the Catholic Church's viewpoint.
SSM Health Dean Medical Group nurses vote to unionize
This comes just a few months after nurses at SSM Health St. Mary’s Hospital voted for union representation.
White House to reopen part of Lafayette Square after eight months
Administration officials are still pursuing plans to build a permanent fence around the park.
Liverpool still chasing in-demand Virgil van Dijk successor
Liverpool are a team in transition, and Andoni Iraola’s squad is a long way from being complete. The Reds have spent over £650 million in the past 18 months, breaking the British transfer record tw...
Turned down MIT for a little-known college. Not everyone understood.
Hannah Mitchell turned down MIT for a the Merchant Marine Academy. Three months in, she says it was the right decision.
Trump dined with the Anthropic CEO who called for AI slowdown
The president’s first one-on-one meeting with Dario Amodei followed months of tensions.
Harbor cleanup removes a health and safety hazard at Hwy 101
GOLD BEACH, OR — Trash and human waste that had been building up for months near the intersection of Highway 101 and Sunshine Cove Lane in Harbor has been cleaned
Brookfield Business (TSX:BBUC) Rebound Hopes Meet A Fair Value Reality Check
Brookfield Business (TSX:BBUC) has been drawing attention after its share price closed at CA$35.96, with recent returns showing mixed momentum over the past week, month, and past 3 months for investors tracking the stock. For context, Brookfield Business is coming off a weak stretch, with the share price down 27.31% year to date and 15.15% over the past 3 months. However, the 3-year total shareholder return of 84.94% still points to a much stronger longer-term outcome than the recent pullback...
Taylor Swift sets new record at MTV VMAs
Taylor Swift is having another good year — just months after her lavish wedding to Travis Kelce, the pop superstar on Sunday made history by becoming the most awarded artist at the MTV Video Music Awards.
Spacecraft burns up in atmosphere after failing to rescue NASA telescope
The robotic spacecraft that failed to rescue an aging NASA telescope has plunged back to Earth, disintegrating in the atmosphere, less than three months after launching on the bold mission.
Rogers Tries to Make El-Sayed’s Health Care Plan Scary
_Taylor, Michigan_HERE’S HOW YOU CAN TELL Mike Rogers is anxious to make up ground in the Michigan Senate race: He held a press conference on health care last weekend. Health care is usually a rough issue for Republicans, because voters associate the GOP with attacking cherished programs like Medicare and Medicaid that Democrats have historically supported. It’s a particularly difficult issue in this campaign, because a few months ago Donald Trump and the Republicans refused to extend temporary financial assistance in the Affordable Care Act. As a result of that decision, more than 20 million Americans faced higher insurance prices this year. That’s not a policy choice you want to be defending at a time when voters frequently cite the cost of health care as a top concern. Throw in the fact that Democratic nominee Abdul El-Sayed can draw on his credibility as a doctor and former public health director in Detroit, and it might seem like Rogers’s best bet would be to avoid health care altogether. But Rogers had his reasons to spotlight health care last Saturday. And they became apparent a few minutes before he spoke, when members of his campaign staff There’s a lot happening. Too much, some days. We can’t promise to have all the answers. But we can promise to keep asking the questions, following the facts, and figuring things out alongside people who care about where this country is headed. Read with us. Learn with us. And when it matters, stand with us. Join the side you’re already on. Join Bulwark+
Bad language: profane Trump brings presidential swearing out into open
President has let rip with swearwords in recent months, redefining norms about acceptable language in public office
A ‘Big Problem’: Trump’s War With Iran Drags Down Republicans in Midterms
As their November picture darkens, and gas and diesel prices soar, some Republicans who backed the war for months are now changing their tune.
Andy Burnham brings good vibes to Labour’s annual conference but tough choices are coming
LONDON (AP) — British Prime Minister Andy Burnham has been in the job for two months, and so far his party isn’t demanding his head. These days, that’s an accomplishment.
Andy Burnham brings good vibes to Labour’s annual conference but tough choices are coming
British Prime Minister Andy Burnham has been in the job for two months, and so far his party isn’t demanding his head. The governing Labour Party opens its annual conference beside the River Mersey i...
Andy Burnham brings good vibes to Labour’s annual conference but tough choices are coming
British Prime Minister Andy Burnham has been in office for two months, and his party seems content for now | KNSS Radio
Zidane fever grips France
In the months between the 2024 Euros and the 2026 FIFA World Cup, there was a malaise that gripped the French public, who became less enamoured and more ambivalent towards their national football team...
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Marseille’s Derek Cornelius set for three-month absence
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Hands-on science can be cool
After spending many long days conducting experiments to find a new way to combat bacterial infections in crops, Misha Hegde and Mia Soleil Maurer have been rewarded with international recognition and access to top research facilities. But these are not typical scientists. They are 16-year-old German high school students.“Our supervisor told us that in order to start a project, you need to begin with either a question or a problem,” says Misha, adding that she and Mia had read about antibiotic resistance in certain plants being treated for bacterial infections. “We found out that antibiotics overuse is very common in agriculture,” explains Mia. “Our aim was to create an alternative to antibiotics and to try to raise awareness of the problem of overusing antibiotics.”Their subsequent research has focused on harnessing bacteriophages, the natural predators of bacteria, to eliminate pathogens threatening food crops treated with antibiotics. At the Schuldorf Bergstraße Jugend forscht MakerLab in Seeheim-Jugenheim, located in the German state of Hesse, they discovered a novel phage that infects the Rhizobium rhizogenes bacterium, which causes the hairy root disease that can reduce yields of tomatoes, carrots, soya beans and other food staples.The students believe their method could curb antibiotic use, while protecting plants from infections without disturbing the natural soil microbiome. “The application of phages is host-specific, so they would only kill the targeted pathogen or disease-causing bacteria,” explains Mia. It may also offer environmental benefits, since applying antibiotics can contaminate groundwater.Getting to this point has not been easy. The childhood friends admit to feeling frustrated when their trials did not yield the expected results. “We spent six months on our first experiment, just doing the same thing over and over and over again, to the point where we thought, is it even worth it? Why are we doing this?” Misha says. “You just need to be brave enough to take that first step and keep going.”The benefits of inquiry-based learningTheir determination has paid off. In 2025, the pair won first prize in biology at Jugend forscht, Germany’s national competition for young people interested in science, technology, engineering and mathematics. They were also among the winners of the German Research Foundation Europa-Preis, which is awarded to selected national winners at Jugend forscht, and took third place in the 2025 European Union Contest for Young Scientists.The Jugend forscht Foundation opens doors for young people to connect with scientists as well as industry professionals. Jessica Bönsch, executive director of the Foundation, sees Misha and Mia as prime examples of how young people can develop a deeper understanding of science through their own research projects. “The experience of working on your own research question is very important,” she explains, adding that “inquiry-based learning engages with real-life problems in a way that can be more motivating than traditional classroom teaching.”The Jugend forscht Foundation offers financial support through sponsor pools in Germany’s federal states. Some projects are developed in cooperation with student research centres, university labs or informal collaborative learning areas called makerspaces. Other activities start as hands-on “garage projects” and can grow within the Jugend forscht network and infrastructure.The Jugend forscht Foundation is also a partner of Science Comes to Town, an EU initiative to strengthen public awareness about science and create bridges between researchers and communities. The EU-financed project involves universities, research institutions and other stakeholders in three host cities — Brest (France), Kiel (Germany) and Split (Croatia).“It's so important for people not to live in a bubble, because I think science can be very scary if you misunderstand it,” Mia says of SCTT. The initiative’s aim of raising awareness about science is “absolutely amazing,” Misha adds. “I think it's the best way to kind of make science digestible for the public. In a world where misinformation in science is getting more radical, more dangerous, becoming more of a threat to the trust in scientific infrastructure and foundations, we need such programmes.”Misha and Mia also believe that SCTT can help break down gender stereotypes in science by encouraging young women to study and pursue careers in scientific fields. Both students have benefited from female mentors and encouragement they had when they were much younger. Mia’s love of science began with a class trip to a lab, while Misha — with a smile on her face — says she wanted to study history until “a teacher kind of coerced me into joining a school science club.”Recognition beyond EuropeIn May, Misha and Mia were among the finalists at the Regeneron International Science and Engineering Fair held in Phoenix, Arizona, and involving nearly 1,700 pre-university students from over 60 countries. “It was very crazy because there were so many people and so many teenagers interested in science,” Mia recalls. The event was also challenging. “It was eight hours of continuously presenting your project,” adds Misha.Attending the fair was a chance for the young women to see first-hand the value of international collaboration as well as how research cultures differ. “America is a bit more willing to take risks, and I think that's something we can learn about here in Europe,” Misha explains. However, she continues, “I think Europe has the talent, has the innovation and has the resources” to be competitive.Misha and Mia plan to continue their phage experiments in the new school year, inspired by the project’s hands-on nature and the support they receive from their supervisors. They have also attracted the interest of professional scientists and received invitations to leading research facilities, including the Centre for Synthetic Microbiology, jointly run by the University of Marburg and the Max Planck Institute for Terrestrial Microbiology in Germany. “It is so cool that we can do something to try to move the world in our school and at this age,” Mia says.After completing secondary school, Mia plans to study microbiology and pursue a career in medical research, focusing on Ebola and other infectious diseases. “This has been my dream for so long,” she says. Her friend Misha is interested in biological research with a focus on medicine. “I've gotten addicted to the process of going to the lab, planning out experiments, then failing, trying again,” Misha says. “I think there's just so much to be discovered, so much to be done.”The students' names and photos were published with the permission of their parents.Science|Business, which connects policymakers, academics and industry through its news reporting, analysis and events, is an SCTT partner.
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Nearly three months after the 24 June 2026 earthquakes in Venezuela, the response has moved into early recovery while sustaining essential emergency operations. Efforts now center on maintaining continuity of care across mental health, sexual and reproductive health, maternal and neonatal care, NCDs, and rehabilitation, alongside restoring affected facilities, supporting transitional camps, and strengthening Health Cluster coordination as Emergency Medical Teams and international partners withdraw. Health system recovery is advancing, with 16 ASICs and 356 health facilities assessed (61% operational) and rehabilitation progressing under CERF, CFE and US funding, while fluctuating electricity, medication refrigeration and emergency-generator gaps continue to challenge the safe continuity of essential health services. Public health surveillance and prevention remain active, with 47,145 cumulative vaccine doses administered and 556 health professionals trained, while intensified surveillance in La Guaira and Miranda and mounting environmental risks from tropical rains and heatwaves continue to require sustained vector-control and water/sanitation action. Contraception remains the most consistent unmet need across assessed shelters, particularly among adolescents and young women, while mental health needs continue to rise across the transitional camps amid limited supplies and specialized personnel. PAHO/WHO continues to support the response with critically needed medical supplies and medicines, having shipped 46.6 metric tons to Venezuela to date, benefiting 72 actors and reaching 117,714 people with treatment through PAHO and partner donations, while sustained technical and logistical support to the Ministry of Popular Power for Health (MPPS) has strengthened the national supply chain and ensured the continuity of health services through the coordination, reception, and mobilization of international donations of essential medical products.
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Christina Applegate shares new video after months in the hospital
Christina Applegate is sending her love to fans after months in the hospital.
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Jiang Feng: The Unravelling of German & European Politics
A state election in eastern Germany has become a revealing test of the changing political landscapes of Germany and Europe, writes Jiang Feng, Professor and Chairman of the Council of the Shanghai Academy of Global Governance and Area Studies (SAGGAS) at Shanghai International Studies University. His analysis follows the decisive victory of the Alternative for Germany (AfD) (which has been classified as right-wing extremist by German authorities)in the state of Saxony-Anhalt on 6 September, in which it finished far ahead of its mainstream rivals. Jiang previously served as Minister-Counsellor at the Chinese Embassy in Berlin. The following article was published on 8 September 2026 on huanqiu.com, the online platform of the Global Times. On 6 September, the results of the state election in Saxony-Anhalt, Germany, were announced. The Alternative for Germany (AfD), classified as far-right by German authorities, made history by becoming the largest party in the state parliament, winning 43.8 per cent of the vote — twice its share in the previous election. The Christian Democratic Union (CDU), which had governed the state continuously for 24 years, won just 17.2 per cent, its worst result ever in Saxony-Anhalt. On the night the results were announced, the atmosphere at the CDU gathering was unusually calm. There was neither shock nor argument, as if the defeat had long been expected. Several veteran party members who had spent years working in the state government said: “Defeat is not a bad thing. It is time to make changes.” This state election has not only upended Saxony-Anhalt’s political landscape, but also laid bare the deep tensions between Germany’s traditional party structure and model of governance, on the one hand, and an increasingly polarised society on the other. Its repercussions are already being felt at the federal level, making Saxony-Anhalt a useful case study of the broader trend towards political polarisation and realignment in Europe. Governing Difficulties after Electoral Victory The most immediate consequence of the election is a historic setback for the mainstream party order that took shape in post-war Germany. In Saxony-Anhalt, the AfD has leapt from a peripheral party to the largest political force in the state. Its electoral base has expanded beyond the traditional category of “marginal protest voters” to take on the characteristics of a cross-class coalition. The party has not only consolidated its support in rural areas, but also attracted many middle-class voters and even members of the social elite with stable jobs, their own homes, and substantial incomes. It has thus evolved from a “protest party” into one with the potential to govern. Despite its commanding lead in the vote, however, the AfD faces an institutional obstacle to governing the state: the mainstream parties’ long-standing “firewall” against it. Neither of the two potential routes to forming a government appears likely to break the current political deadlock. The first would be a coalition of establishment parties, led by the CDU and bringing together the Social Democratic Party (SPD), the Greens, the Left Party (Die Linke) and the Sahra Wagenknecht Alliance (BSW) in a cross-camp government. In terms of parliamentary arithmetic, such a coalition could prevent the AfD from forming a government and preserve the outward stability of the traditional political order. Yet these parties are fundamentally divided over key issues including immigration, the energy transition, economic management, and cultural and education policy. Coalition negotiations would therefore be extremely difficult, and even if a government could be formed, it would most likely prove short-lived. More importantly, an alliance of establishment parties aimed at keeping the largest party out of government would play directly into the AfD’s narrative that “political elites are suppressing public opinion”. It could deepen perceptions of political unfairness, further strengthening the AfD’s political capital, and creating a dynamic in which “the more it is suppressed, the more people vote for it”. Ulrich Siegmund, the AfD’s candidate for state premier, has said that if efforts to form a government fail because other parties refuse to cooperate, the AfD will push for a fresh election, which he believes could deliver the party an absolute majority of seats. This points to more intense political battles ahead. The second option would be a coalition between the AfD and the BSW. Together, the two parties would command a simple majority in parliament, making this, on paper, the quickest route to forming a government. The BSW is the only elected party that has not ruled out cooperation with the AfD, and the two parties share some common ground, including on policy towards Russia. There is therefore a degree of political basis for cooperation. Were such a coalition to materialise, Germany would see its first state government jointly formed by a party defined as far-right and one with a far-left background, creating what might be called a “bipolar anti-establishment alliance”. Such an outcome would fundamentally break with the ideological boundaries of post-war German party politics. It is worth noting that even if the AfD ultimately fails to enter the state government, its roughly 47 per cent share of parliamentary seats would give it a powerful blocking minority. Without its consent, major decisions requiring a two-thirds majority — including constitutional amendments, significant budgetary adjustments, and state-level institutional reforms — would be extremely difficult to pass. Therefore, whoever ultimately forms the government, the AfD will be an unavoidable force in Saxony-Anhalt politics, with a direct influence on the state’s legislative process. Systemic Failures in Germany’s Governance Model The Saxony-Anhalt election result reflects a systemic failure of Germany’s post-war mainstream-party model of governance to adapt to rapidly changing socioeconomic conditions. It stems from multiple, mutually reinforcing structural tensions and highlights the existing political system’s difficulty in adapting to “an increasingly polarised society First, collective anxiety has replaced individual material hardship as a central driver of political mobilisation. The rise of the AfD can no longer be explained simply by poverty or social marginalisation. Its increasingly cross-class electoral base suggests that what is driving voters towards the party is, above all, concern about the broader direction of society. This anxiety about the future of the political community goes beyond individual gains and losses. In political discourse, economic anxiety has become closely intertwined with immigration, while immigration and refugee issues are, in essence, questions of social fairness. This perception turns conflicts over the distribution of social resources into negative assessments of governing parties, providing a broad social basis for far-right political narratives. Second, regional disparities and East German identity have undermined the strategy of addressing eastern Germany’s structural challenges at the regional level. More than three decades after German reunification, eastern states such as Saxony-Anhalt have experienced periods of economic growth, but their underlying economic structures remain weak, and household incomes and wealth remain significantly below those in western Germany. At the same time, they continue to face population outflow, an ageing population, labour shortages, and other structural challenges. At a deeper level, historical experiences — including the collapse of the former East German economic system, mass unemployment during the transition, and the westward shift of decision-making power over major issues — have left some residents with a sense of being “second-class citizens” and of being excluded. For years, the German government treated the “syndrome” of reunification as a regional problem to be gradually addressed at the local level. That approach is becoming increasingly unsustainable, as regional development disparities emerge as a core structural factor shaping national politics. Third, the erosion of institutional trust is perhaps the most decisive factor. AfD supporters tend to distrust establishment institutions, including parliament, government, and the mainstream media. Their concerns about economic security, pensions, and social fairness are significantly greater than the social average. Increasingly, their support for the AfD reflects not an expectation that the existing system can be improved, but a search for an alternative to the current political order. Such a systemic deficit of trust will be extremely difficult for the traditional parties to repair in the short term. Fourth, a generational shift in political mobilisation has amplified political polarisation. Unlike traditional parties, which rely heavily on offline rallies and mainstream media coverage, the AfD has developed a social-media mobilisation strategy built around “raising an issue — identifying who is responsible — offering a simplified solution — building a shared identity”. It turns complex social tensions into concise political narratives, rapidly channelling public sentiment into political support. The contrast on the eve of the election was particularly telling. The establishment parties, together with trade unions and churches, organised an offline march attended by more than 10,000 people, but its reach was largely confined to those present and to traditional media coverage. The AfD held a much smaller indoor event, yet livestreaming on TikTok, YouTube, and other platforms, combined with the involvement of online influencers, gave it a reach and mobilising capacity far beyond that of the march. The contrast illustrates how the traditional parties’ methods of political mobilisation are increasingly struggling to keep pace with a political environment transformed by changes in media technology. A Microcosm of Structural Political Change in Europe The shockwaves from the Saxony-Anhalt election quickly travelled beyond the state to the federal level. Calls for political accountability followed immediately after the results were announced. The governing CDU and SPD are now under enormous pressure, while Chancellor Friedrich Merz and Vice Chancellor Lars Klingbeil face an unprecedented test. Political polarisation in Germany is no longer simply a regional phenomenon. The post-war model of multiparty government by establishment parties is breaking down and being reshaped. Viewed in a broader European context, the Saxony-Anhalt election is part of a continent-wide wave of party polarisation, mainstream-party decline, and rising right-wing forces. Far from an isolated phenomenon, it is a microcosm of the structural political changes unfolding across Europe. Weak economic growth, cultural tensions over immigration, and declining trust in institutions are fuelling the rise of right-wing forces in several countries, challenging the liberal internationalist order established in post-war Europe. As a core member state of the European Union, Germany’s ability to adapt its political system and the direction of its politics will have profound implications for both European integration and the evolution of the international order. Subscribe [ Pekingnology China’s Germany watchers take stock of Berlin’s uneasy turn On 7 December 2025, nearly 50 Chinese scholars and policy researchers gathered in Beijing for the 2025年德国形势年终研讨会 “2025 Year-End Seminar on the Situation in Germany… Read more 9 months ago · 31 likes · 1 comment · YIRUI LI and Yuxuan JIA ](https://www.pekingnology.com/p/chinas-germany-watchers-take-stock?utm_source=substack&utm_campaign=post_embed&utm_medium=web&embedding_publication_id=1151841) [ Jiang Feng on Germany's 2025 and beyond: no easy exit ](https://www.eastisread.com/p/jiang-feng-on-germanys-2025-and-beyond) Yirui LI and Yuxuan JIA · Jan 24 The following is an op-ed by Jiang Feng, published on 29 December 2025 at Shanghai Observer 上观新闻, the digital platform of Jiefang Daily, the official newspaper of the Shanghai Municipal Committee of the Communist Party of China (CPC). [ Read full story ](https://www.eastisread.com/p/jiang-feng-on-germanys-2025-and-beyond)
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