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At Family Science Night, Wonder Comes Before Answers.
BAR HARBOR—Family Science Night isn’t really about science. It’s about wonder. It’s about watching a five-year-old realize that the tiny creature under a microscope is a real living thing. It’s about a teenager discovering that the scientist explaining genetics or regeneration isn’t much older than they are. It’s about parents seeing curiosity spread across a child’s face the way excitement spreads across a crowd at a Fourth of July parade. For one evening, families realize that the laboratory isn’t some secretive place where knowledge is hidden behind white coats and closed doors. They learn that the lab is a place their neighbors work, their friends’ parents work, and it becomes a place where questions matter more than answers. It’s a place where wonder is the origin for knowledge. At the lab, children learn that it’s okay not to know. Adults remember that they once asked “Why?” about everything. Scientists are reminded why they fell in love with discovery in the first place. There are experiments, games, obstacle courses, and demonstrations, of course. But those are really just invitations—to touch, to explore, to laugh, to make mistakes, and to ask one more question. In a world that often rewards certainty, Family Science Night celebrates curiosity. And perhaps that’s its greatest gift. Long after the microscopes are packed away and the experiments are over, what families take home isn’t just a few new facts about biology. They take home the feeling that discovery belongs to everyone—that science isn’t something happening somewhere else by someone else. It’s simply what happens when people are given permission to wonder. A Family Science Night at the Mount Desert Island Biological Laboratory is one of those rare community events where children and adults can experience science as something they do, not just something they read about. Hands on discovery allows hands-on learning and joy. Real scientists, some local, some scientist-interns (but still scientists) just in college make science real, approachable, and exciting. And there, complex ideas like forever chemical-filtration, DNA and so much more become not complex. Instead, they become fun. Summer fellows are challenged to explain cutting-edge biomedical research in ways a first-grader—and their grandparent—can understand. Past activities have explored gene expression, kidney function, axolotl regeneration, worms, microplastics, and phytoplankton through games and creative demonstrations. Though it’s called family night, you can also see adults going from station to station, exploring, learning together across ages. Family Science Night reflects the laboratory’s broader mission of breaking down barriers between researchers and the public, helping people understand how scientific discoveries relate to everyday life and the health of Maine’s environment. Family Science Night transforms a world-class research laboratory into a giant interactive classroom, where curiosity is encouraged, questions are celebrated, and families discover that science isn’t just something that happens in a lab—it’s an adventure anyone can join. About MDI Biological Laboratory For more than 125 years, MDI Bio Lab has been a center for training and research in comparative biology. In the last two decades its biomedical research has focused on aging, regeneration, and environmental toxins. The Laboratory houses 11 research groups staffed by an international team of world-class scientists and graduate students. It also leads a statewide network of colleges, universities and research institutions that collaborate to provide training, research experiences and financial support to help young Mainers play a bigger role in today’s biomedical revolution. Located on Maine’s rugged coast, the Laboratory’s 100+ acre campus houses research facilities, cottages and dorms that house visiting scientists and students. It is also home to MDI Bioscience, a subsidiary working to design innovative techniques to speed the drug discovery process. LINKS TO LEARN MORE NIH INBRE MDI BIOLOGICAL LABORATORY Photos: Carrie Jones and Shaun Farrar/Bar Harbor Story HELP SUPPORT THE BAR HARBOR STORY When we started The Bar Harbor Story, we didn’t know if anyone would read it. But you showed up. You shared. You sent tips. Now—over 400,000 views every month later—it’s clear: people here care about their community and each other. We’ve kept everything free because news should never be out of reach, but every one of our stories takes time to write, and your support keeps The Bar Harbor Story going. If you value our work, please consider a paid subscription, a founding membership, or a sponsorship. It truly helps us cover one more meeting, tell one more story, shine one more light. Even $5 a month makes a difference. Click here to become a one-time supporter now. Thank you so much for being here. Founding member information can be found here. Have questions about sponsorships? Just send Shaun an email at sfarrar86@gmail.com, he’d love to hear from you. Subscribe Share Bar Harbor Story Share Leave a comment
Microsoft wants to integrate your smartphone more deeply with Windows 11: Plans major UX enhancements that will make your PC and phone more seamlessly connected
Sources say that Microsoft is exploring several ways it can introduce new smartphone integration features across the Windows 11 interface in the coming months.
Poll: Home Run Derby or All-Star Game?
Editor's note: Welcome to Athlon Sports' poll of the day, where we ask readers to weigh in on the biggest topic of the day. Thanks for voting, and be sure to sound off in the comment section. We've got one more day of baseball action before most of the MLB's players get to relax during the all-star break.
What smart people are saying about Apple's lawsuit against OpenAI
Apple sued OpenAI on Friday, accusing the AI startup of orchestrating a campaign to steal trade secrets from iPhone maker.
The First Test of Bar Harbor's New Entertainment Rules.
The Bar Harbor Story is generously sponsored by the Bar Harbor Historical Society. BAR HARBOR—The Finback Alehouse was the first real test of the town’s new special amusement permit process, July 7 while eight other permits sailed through the process last week. The permit allows music in places where liquor is served. The town’s ordinance which was recently tweaked for a new process allows for the regulation of noise and hours of activity. The only discussion at the July Town Council meeting was about the Finback Alehouse on Cottage Street, in the heart of Bar Harbor’s downtown district. The Finback’s distinctive design—a front wall that is like a garage door that can be opened and closed—was a key to that discussion. The restaurant, which often hosts live bands, singers, and karaoke, at night, has had one substantiated noise complaint this season, which is documented on its application. According to Bar Harbor Police Chief David Kerns, most complaints about noise happen after 10 p.m., and if the Finback had two more violations within a year, they’d have to stop having music. One town councilor said that he’d have no problem reissuing the permit if the door was down. The permit passed through the process with no conditions. Vice Chair Earl Brechlin moved the motion with two time changes for two holiday weekend dates. It passed unanimously. The council asked the Finback why they’d chosen an indoor license with a wall that can be opened to the street. Dale Stockburger, representing the Finback, said he’d applied for an indoor permit rather than an outdoor structure or partial structure (which is usually applied to tents or pavilions). The restaurant has traditionally had an indoor license. Stockburger said that whether the door is open or closed is immaterial because he now stands outside with a decibel reader to make sure that the music isn’t too loud. OTHER SPECIAL AMUSEMENT PERMITS New Councilor Deborah Vickers worried that she had potential conflicts of interests on two other renewals due to the location of her employee housing. Vickers co-owns the Black Friar Inn. They have employee housing directly behind the Finback, which is also 300 yards from the Bar Harbor Inn, she explained. The Bar Harbor Inn also had a permit up for renewal. The councilors unanimously voted she did not have a conflict of interest. The councilors approved permits at The Bluenose Inn, 90 Eden St, Class A; Acadia Hotel Downtown, 20 Mount Desert St, Class A and C; the Bar Harbor Inn, 8 Newport Dr, Class A, B, C and D; C-Ray Lobster, 882 State Hwy 3, Class D; Holiday Inn Bar Harbor Regency, 123 Eden Street, Class B; Finback Alehouse, 30 Cottage St, Class B; Project Social, 278 Main St, Class C and D; Bar Harbor Beer Works, 119 Main St, Class B and D; and Mainely Meat BBQ Dreamwood Hill, 369 State Hwy 3, Class D. That process is laid out in the Special Amusement Ordinance of the Bar Harbor Town Code which is Chapter 14 of the town code. Special amusement permits have class codes. These are the meanings: Number - how many musicians are allowed by the permit. Class A - Indoor non-amplified entertainment. Class B - Indoor amplified entertainment or dancing. Class C - Outdoor non-amplified entertainment. Class D - Outdoor amplified entertainment. RESIDENCE LICENSES RENEWED AND A TAXI LICENSE The councilors also renewed the licenses for three specific sorts of residences that require that yearly renewal per the town code. The employee living quarters at Atlantic Oceanside Hotel, 119 Eden St and another at 278 Main Street were renewed. The shared accommodations license renewal at 39 Kebo Street also occurred. These are annual renewals. Bernard Taxi Services’ license was also renewed. This license had been added to the agenda at the meeting. Bar Harbor Update on Leaf and Grass Clipping Disposal BAR HARBOR — Bar Harbor residents will still have a place to throw away their leaf and grass clippings this summer. The town’s agreement with EMR in Southwest Harbor for disposing of those items will continue through November 30. The agreement, according to a town press release, will continue “while the Town continues evaluating long term composting solutions and the required state permitting process.” As of July 1, residents bringing their grass and leaves across the island to the facility in Southwest Harbor will have to fill out a property registration card. Each property can throw out up to 85 pounds of the grass and leaves. “Any disposal exceeding the 85 pound allowance during this period will be the responsibility of the property owner at the applicable disposal rate,” the press release explains. LINKS TO LEARN MORE Watch the meeting Meeting agenda QUICK NOTE: We’d released the Bar Harbor Leaf information as a brief, but wanted to make sure that people saw it, so we’ve included it here, too. HELP SUPPORT THE BAR HARBOR STORY When we started The Bar Harbor Story, we didn’t know if anyone would read it. But you showed up. You shared. You sent tips. Now—over 400,000 views every month later—it’s clear: people here care about their community and each other. We’ve kept everything free because news should never be out of reach, but every one of our stories takes time to write, and your support keeps The Bar Harbor Story going. If you value our work, please consider a paid subscription, a founding membership, or a sponsorship. It truly helps us cover one more meeting, tell one more story, shine one more light. Even $5 a month makes a difference. Click here to become a one-time supporter now. Thank you so much for being here. Founding member information can be found here. Have questions about sponsorships? Just send Shaun an email at sfarrar86@gmail.com, he’d love to hear from you. Subscribe Share Bar Harbor Story Share Leave a comment
New England Patriots’ Defense Still Has One Major Blind Spot
The New England Patriots spent the offseason strengthening a defense that already finished fourth in the NFL in points allowed.They added talent around Christian Gonzalez, Carlton Davis and Milton Williams, in addition to reshaping the linebacker room and continuing to build the type of fast, physical unit head coach Mike Vrabel prefers.There is still one […] The post New England Patriots’ Defense Still Has One Major Blind Spot appeared first on HEAVY.
Ryse: Son of Rome Is Now Just an Xbox One Memory, but in 2013 It Was Planned To Be an Era-Hopping Franchise To Rival Assassin’s Creed’s Global Ambition
Ryse: Son of Rome was originally planned to explore multiple eras, Assassin's Creed style, before critical and commercial failure sank Crytek and Xbox's ambition.
Phil Weiser’s sudden need to find the brake pedal
Indulge me with a personal story at the outset. Trust me, it relates. Years ago, when our kids were young, we briefly had a small jalopy for a babysitter’s use. One morning, I discovered that the battery on this poor excuse for a car was dead. Our driveway sat on a bit of an incline, […]
World Cup: After Thibaut Courtois’ injury, one mistake sent Belgium home and Spain through
A 58-year-old Texan bet $430,000 of retirement funds on a golf franchise — and the business was profitable in one month
From boredom in retirement to the pursuit of higher investment returns, older Americans are launching businesses instead of settling into traditional retirement.
Last Call: M5 Pro MacBook Pro Remains at Pre-Hike Price But Not for Much Longer
It's been a few weeks since Apple announced widespread price hikes across numerous product categories, including the 2026 MacBook Pro. These new prices are now reaching third party retailers, but there remains one exception at Best Buy, which still has one model of the 14-inch M5 Pro MacBook Pro at its pre-hike price. Note: MacRumors is an affiliate partner with Best Buy. When you click a link and make a purchase, we may receive a small payment, which helps us keep the site running.
'Siri AI' Lawsuit Update: Apple to Pay Owners of These iPhone Models
In May, Apple agreed to pay $250 million to settle a U.S. class action lawsuit over Siri AI's delayed launch, and eligible iPhone users could receive up to a $95 payout. This week, the California court overseeing the case held a hearing regarding preliminary approval of the settlement, but the judge has not yet issued a ruling.
Union Backs Family Physician After Logan Health Lets Contract Lapse
As a group gathered inside the Logan Health Glacier Conference Center Tuesday evening, Tim Jenkins, the chief negotiator for the Union of American Physicians and Dentists (UAPD), began the meeting with a Bible verse from Ecclesiastes. “‘And where one may be overpowered, two can stand their ground, a cord of three is not quickly broken,’” […]
Business travellers are carrying the office everywhere they go, according to Holafly for Business's latest research
Corporate eSIMs for Business Travel Holafly A modern professional stays securely connected on the go. According to Holafly for Business, 81.3% of travellers report a positive impact on productivity when using a corporate eSIM. Today, business travel is about carrying your entire working environment with you. DUBLIN, July 09, 2026 (GLOBE NEWSWIRE) -- The modern business trip looks very different from the one most companies designed their travel policies around. Airports have become workspaces, ho
Gallery of Studio Gang and Henning Larsen Complete One Milestone Life Science Campus in Boston - 1
Image 1 of 23 from gallery of Studio Gang and Henning Larsen Complete One Milestone Life Science Campus in Boston. Photograph by Jason O'Rear
Computer Science Alum Pair Gains Key Experience Overseeing Data Science Projects as BU Spark! Postbaccalaureate Fellows
Learn how a pair of MET CS alums—one MS in Software Development alum and one who earned a MS in Computer Science with a concentration in Data Analytics—got vital experience overseeing data science projects as postbaccalaureate fellows in the BU Spark! program.
Ancient DNA reveals the mysterious collapse of Europe's megalith builders
DNA from a 5,000-year-old French megalithic tomb reveals that the people buried before and after a population collapse were genetically unrelated, pointing to a major migration after a devastating crisis. The shift coincided with new social traditions and the disappearance of the communities that built Europe's giant stone monuments.
Samsung to Get Jump on Apple’s First Foldable With New Phones in July
Samsung Electronics Co. will host its next Galaxy Unpacked event on July 22, when the leading foldable phone maker is expected to unveil a Galaxy Z Fold 8 with a shorter and wider design that resembles Apple Inc.’s planned folding iPhone.
Nikola Jokic Gives Update Every Nuggets Fans Needed Amid Contract Talks
Jokic says he's staying in Denver, and he explained exactly why he's willing to wait one more summer to make it official.
Google Pixel 11 Leak Hints at Higher Prices, New Colors and More Storage
While Google's official Pixel 11 unveiling is next month, several key features of the next Android phone may have been revealed early.
Foldable iPhone Ultra vs. iPad: How their screens reportedly compare
When opened, the foldable iPhone may scratch users' iPad itch too.
For a Georgia entrepreneur, health coverage has never been affordable
Amy Bielawski is one of the 30 million people who run their own businesses. She's gone most of her life without health insurance.
For a Georgia entrepreneur, health coverage has never been affordable
Amy Bielawski is one of the 30 million people who run their own businesses. She's gone most of her life without health insurance.
The foldable iPhone may be in short supply upon release
The expected iPhone Ultra's advanced design is likely to pose challenges for manufacturing.
What one Mass. blueberry bush tells scientists about climate change
The bush has been growing here since the observatory’s founding in 1885, if not longer. For 141 years, without missing a season, observers at Blue Hill have recorded the date when the first berry ripens. Their data provide a unique picture of the effects of a warming climate, and its impact on one of New England’s favorite summer treats.
Celtics could flip Paul George to add $112 million wing in another blockbuster
The Boston Celtics shocked the NBA world with their recent Jaylen Brown trade, but it's possible the team isn't done making moves.
Man killed, another injured in late-night shooting outside North Austin business
Police are investigating a late-night shooting that left one man dead and another injured in north Austin, marking the city's 32nd homicide of the year.
Statues of US presidents' heads are crumbling in rural Virginia
After a Virginia park closed 2010, one man saved 42 presidential statues from being crushed. Now, they're a massive tourist attraction.
iPhone Fold could help raise average foldable phone prices by 18%
Apple’s entry into the foldable smartphone market will reportedly be one of the factors driving an 18% increase in average sale prices in the category in 2026.
ESPN Grades Detroit Lions Offseason
ESPN gave the Detroit Lions one of the NFL's highest offseason grades, praising Brad Holmes' work while questioning one major move.
Apple to launch 5 new iPhone models to gain market share amid memory crunch
Company raises production target for first foldable phone to about 10 million units
iPhone Fold expected to fuel rebound in foldable phone panel shipments
Apple’s entry into the foldable phone market will help drive a strong rebound in foldable smartphone panel shipments this year.
Only one Minnesota Viking makes CBS Sports' top 100 NFL players for 2026
AirDrop is finally coming to Motorola, but only to one specific smartphone
One more Android brand is getting AirDrop support over Quick Share.
“Supergirl” is a decent standalone movie — so why is everyone acting like it’s awful?
Despite what the reviews and backlash may lead you to believe, the second film in the DC Universe is an enjoyable adventure.
'Supergirl' is a decent standalone movie — so why is everyone acting like it’s awful?
'Supergirl' has been in theaters for less than a week, and it seems everyone is quick to call it a failure after a disappointing opening weekend at the box office. But does it actually deserve the backlash it's receiving?
LeBron James leaving Lakers, reportedly plans to return for 24th NBA season with a new team
James will continue his run of unprecedented longevity and production for at least one more season.
I Tried Sony's $260 Wearable AC. Here's Why I Turned Around Before Leaving the Block
Sony's Reon Pocket Pro Plus delivered on its promise of keeping me cool—but one major flaw made wearing it in public surprisingly difficult.
Studio Gang and Henning Larsen Complete One Milestone Life Science Campus in Boston
Studio Gang and Henning Larsen's One Milestone brings life science labs, flexible workspaces, and public amenities to Boston's Allston neighborhood.
How 'masculinism' is reshaping American politics
Can the new faultline in American political tribalism be broken down along the masculine question? Republican attacks against Texas Democratic Candidate for Senate James Talarcio falsely claim he's vegan as a challenge to his masculinity. While others in the GOP say they want to repeal the Woman's right to vote. What is he overarching strategy here. Why testosterone matters in today's politics.
Laser weapons aren’t science fiction anymore — and they’re changing how defense stocks are valued
Why Palantir and Elbit are top plays in the booming counter-drone market.
Is this World Cup now Europe v South America? Which giants fall today? Day 18 recap
Sunday was the strangest day of this World Cup, in that there was only one match, sandwiched between days with six and three respectively. This was for scheduling reasons: no third-placed sides could have played on Sunday, given that the identity of the eight sides and their precise fixtures had only been decided on Saturday night. It would also have been impossible to organise fixtures between any other winners and runners-up while also giving them a reasonable — and relatively similar — number of days since their final group stage fixture. In the game that did happen, co-hosts Canada...
Anxiety drives child mental health referrals past one million
Demand is soaring beyond capacity, meaning children in England wait years for help with various conditions.
Efzimfotase alfa demonstrated improvements in bone health in treatment-naïve pediatric patients with hypophosphatasia achieving median difference of 1.67 vs placebo in RGI-C Score at week 25 in MULBERRY Phase III trial
Positive results from the MULBERRY Phase III trial showed that efzimfotase alfa (ALXN1850), an investigational enzyme replacement therapy, demonstrated a statistically significant and clinically meaningful improvement in bone health in children (2 to
Kerry loss 'will take a while to get over'
Tyrone midfielder Conn Kilpatrick says the 2-25 to 0-27 All-Ireland SFC quarter-final defeat by Kerry will "take a while to get over".
Inside country legend Alan Jackson\'s triumphant finale concert
Country music legend Alan Jackson has ended his touring career. On Saturday night, he performed his final show at Nashville's Nissan Stadium. The event, titled “Last Call: One More for
4 AI Prompts to Build a Profitable One-Person Business in 2026 (The Part Every AI Influencer Skips)
Spot the one move every AI influencer skips — and turn it into your next multimillion-dollar business.
Seattle ups its payout for vandalized small businesses. Is it enough?
For many businesses, the reimbursement "could be the difference between someone making their rent or not, just because this is such a tough time,” said Analog Coffee's owner.
What could be next for Gakpo?
Following the departure of Mohamed Salah, at least one more attacking signing is expected at Anfield this summer. Liverpool have already signed Victor Munoz from Osasuna for £34.5m and the pursuit of Yan Diomande is heating up. Talented teenager Rio Ngumoha is also set to play a more prominent role, while Florian Wirtz played off the left for Liverpool at times last season and is featuring there for Germany in the World Cup.
EVA HENRY: Corruption resurfaces in Adams, Arapahoe County politics linked to One Main Street
Corporate dark money groups are funneling millions into eleven different races statewide.
Apolosign Digital Calendar and Portable TV for Family Organization and Home Entertainment
NEW YORK, June 25, 2026 (GLOBE NEWSWIRE) -- Apolosign, a smart family display brand serving more than one million households worldwide, today an...
Dolly Parton Makes Surprise Appearance Following Health Issues
Dolly Parton made a surprise appearance at the grand opening of her travel stop in Tennessee just one month after she canceled an upcoming Vegas residency due to health concerns.
How wearable tech aims to innovate women's health care
Clair Health co-founder and CTO (Chief Technology Officer) Abhinav Agarwal comes on Asking for a Trend to explain how the company is using AI models in its hormone monitoring device and how new doctors, specifically OBGYNs, can use it to learn more.
White Sox Have One Clear Trade Deadline Priority
The Chicago White Sox have one major issue they need to address before the MLB trade deadline.
Christian Gonzalez Could Force Patriots Into Awkward Training Camp Standoff
There are no official deadlines in late June or early July in the National Football League. In New England, though, all eyes remain on the Christian Gonzalez contract situation and whether or not he becomes the next young, budding defensive superstar to be rewarded with a mega-deal. Gonzalez, the team’s first-round pick in 2023, has one Pro Bowl and one monster playoff run that has people talking about him like he's an elite corner.
The Carriage House at Paper Mill Playhouse Launches Summer 2026 Entertainment Series
(MILLBURN, NJ) -- The F.M. Kirby Carriage House at Paper Mill Playhouse announces its inaugural Summer Entertainment Series, introducing acclaimed Broadway and cabaret artists Evan Tyrone Martin (New York City Center's The Wild Party) and Annie Hägg (Giant) to lead an expanded lineup of live entertainment throughout July and August at the newly refurbished restaurant and event space.
iOS 27 will add inline replies & photo reactions to Android-iPhone RCS
iOS 27 will introduce the next big update to Android-iPhone messaging with support for inline replies and photo reactions.
PWHL adds Kilmer Sports Ventures, Ilitch Companies as first outside investors
Just one month after completing its third season, the Professional Women’s Hockey League has added its first outside investment, the league announced on Monday morning. Kilmer Sports Ventures, which is led by Toronto businessman Larry Tanenbaum, and Ilitch Companies, the parent company of the NHL’s Detroit Red Wings and MLB’s Tigers, have joined the league as partners. Since its inception, the league has operated under a single-entity ownership model, meaning Mark Walter — the billionaire owner
Buying a Used iPhone Makes More Sense Than Ever
With Apple raising prices soon, you can save a lot of money by buying a used handset or upgrading an older device—safe in the knowledge that it'll last longer than ever.
Panthers defender sets mind-blowing goals for 2026 season
Panthers CB Mike Jackson is looking to go where only one man, at least officially, has gone before.
Health Care Roundup: Market Talk
Find insight on Top Glove, BeOne Medicine and more in the latest Market Talks covering the health care sector.
More than 1 billion barrels of oil have gone missing
The good news: The Strait of Hormuz is open again, after Iran and the United States signed a memorandum of understanding this week.
IOM Conducts Over 1 Million Health Screenings, Scales Up Ebola Response
Geneva/Nairobi 19 June 2026 – The International Organization for Migration (IOM) has conducted more than one million health screenings at borders and along key cross-border routes and travel corridors across Ebola-affected and at-risk countries as it scales up its efforts to support the control of an outbreak that has spread across eastern Democratic Republic of the Congo (DRC) and Uganda.
Who is 49ers most essential non-QB?
The 49ers have a lot of important players, none more essential than these two.
iPhone Ultra final design shared by Apple’s nemesis
Despite the ongoing legal battle, leaker Jon Prosser has been active in sharing leaks and renders for upcoming iPhone models. His latest could very well be the final version of the iPhone Ultra.
World Cup 2026: Austria nabs win over Jordan after handball and own-goal drama
Austria had a go-ahead goal taken away, then got another one minutes later.
Apple's 2028 iPhones to Use 1.4nm A22 Pro Chips
Apple will transition from 2-nanometer chips to 1.4-nanometer chips with the high-end 2028 iPhone models, reports Bloomberg. Chip supplier Taiwan Semiconductor Manufacturing Co. (TSMC) will make the majority of Apple's A22 Pro chips, but Apple is also considering having Intel make some of them. The current iPhone 17 models use a third-generation N3P 3-nanometer process.
Two Women, One Mission: Closing the Gap Between Cancer Science and Survival
A journalist-turned-advocate and a physician-scientist unite at the Parker Institute for Cancer Immunotherapy to accelerate cancer vaccines from lab discovery to lifesaving treatment.
Bonnie Tyler wakes from coma 1 month after emergency intestinal surgery, but remains 'very unwell'
'Total Eclipse of the Heart' singer Bonnie Tyler is awake one month after being placed in an induced coma to aid her recovery from emergency surgery.
How one millennial hit financial independence in three years
"The biggest factor by far, bar none, is the gap between your income and your expenses," says Cody Berman, who hit financial independence at age 25.
Menopausal hormone therapy linked to stronger bone health
Women on menopausal hormonal therapy face a decreased risk of low bone mineral density compared to those not using it, according to a study being presented Sunday at ENDO 2026, the Endocrine Society's annual meeting in Chicago, Ill.
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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