SCROLL NEWS / DISCOVERY
Search headlines
Find the stories shaping the conversation.
Results for " Aster " 6,745 found 🔀 AI-powered Shuffle
How to help wildlife after a nor’easter
Always check fallen trees for animals before chopping them up.
Trump’s mail voting crackdown tests Postal Service leader who says he’s ‘not political’
During a lengthy interview, David Steiner seemed surprised at points by his reception in Washington. He insisted he wasn’t a “political person” and said he had no intention of stepping down despite the criticism. He dismissed heated congr…
DRC politician beaten to death after radio appearance about Ebola outbreak
Marie-Celestin Karondwa was attacked on Sunday after promoting measures to prevent spread of disease, his party says
Dawg Sports on the Radio
There’s a lot to talk about regarding Georgia’s 41-13 win over Oklahoma. It should be a pretty fun conversation. That’s why I’ll be listening to the glockenspiel player from MaconDawg’s favorite U2 cover band (UAndYourMama2) on WFOY in St. Augustine(102.1 FM/1240 AM) this evening around 6:45 pm Eastern to talk Georgia Bulldog football on SportsNow with […]
Every Upgrade In ‘The Witcher 3: Wild Hunt
'The Witcher 3: Wild Hunt - Remastered' is out Sept. 29, and now we have the full patch notes for everything that has changed in the game.
Baobab Fare owners open food truck-inspired restaurant in Eastern Market
The opening comes more than two years after the concept was announced.
Staff killed and wounded in Russian strike on Kyiv’s science academy
Moscow’s jet-powered drones pummel Ukraine’s capital in switch to daytime attacks
Business Monday: Natural disasters devastated some Big Island business, while boosting income for others
Hawai‘i County Mayor Kimo Alameda said it’s an “unbelievable yin-yang story” as some businesses have been forced to shutter while others are thriving.
‘Starship is in orbit’: cheers go up as huge SpaceX rocket circles Earth for first time
Mission goes ahead despite some fears an initial engine failure after the Texas launch would scupper the attempt
President Trump to announce $15 billion steel plant in eastern Iowa
Republican President Donald Trump will announce that Mesabi Metallics will invest $15 billion into building a steel plant in eastern Iowa.
Slipknot to perform in Hershey next summer; here are the details
Heavy metal band Slipknot recently announced a stadium tour, and Hershey is one of its planned stops in 2027.
Mastercard, Sheryl Sandberg, Eric Schmidt Back Small-Business Finance Platform
Mona, an AI-powered finance platform for small business, just raised $3.5 million in funding.
Scientists Pinpoint a Possible “Sweet Spot” for Life’s Origins 4.33 Billion Years Ago
By simulating a billion years of Earth’s history, researchers have identified a possible window for life’s earliest chemistry around 4.33 billion years ago. During its first few hundred million years, Earth was a hostile target. Asteroids, comets, and leftover planetesimals, smaller bodies remaining from planet formation, relentlessly battered the planet, generating intense heat that could
Citizens Bank of Edmond Partners with Parlay to Power Small Business Lending at ROGER, Its Digital Bank for the Military Community
EDMOND, Okla. & ALEXANDRIA, Va., September 28, 2026--Citizens Bank of Edmond partners with Parlay to power small business lending at ROGER, opening a faster path to capital for the military community.
KU School of Education & Human Sciences launches online master’s in higher education administration
The University of Kansas School of Education & Human Sciences is launching a fully online M.S.E in Higher Education Administration housed within the Department of Educational Leadership & Policy Studies. The program builds on KU's established in-person higher education administration graduate degree.
CD Projekt Releases Official List of All the Improvements in The Witcher 3: Wild Hunt
CD Projekt has released an official list of all the improvements made for The Witcher 3: Wild Hunt — Remastered.
Larissa Waters steps down as Greens leader due to ill health
Ballot for new leader expected next week after Waters quits to manage pre-existing kidney disease that has ‘declined significantly’
Job interviews are a weird business
Given the biased nature of the interview process, the recent kerfuffle about taking iced coffee in with you may be the least of our worries, writes Emma Beddington
Salesforce and Innovation City Launch AI-Powered Business Registration Platform
The new implementation combines AI platform capabilities powered by Salesforce with Innovation City's digital ecosystem, enabling businesses to access services and complete registration processes faster through more responsive interactions, while operating within Innovation City’s established governance and regulatory framework.
Dave Nissley and Dale Hamby vie for 100th House District seat
Republican Dave Nissley and independent Dale Hamby have at least one thing in common: Both have run unsuccessful campaigns to represent southern Lancaster County in the Pennsylvania House of Representatives.
PSA: The Witcher 3 Remastered File Size And Release Time Confirmed, Separate Purchase Required
No automatic upgrades here
No solid evidence daylight savings time affects mental health, researchers find
Some people experience effects similar to minor jet lag, but no association with significant declines in mental health, study shows
Phillies Broadcaster John Kruk Gets Postseason Assignment
It took 162 days, but the Philadelphia Phillies were able to clinch their spot in the playoffs. They’ll be the No. 6 seed, just barely making it in the field, which means they’re opening with the Atlanta Braves, who earned the No. 3 seed.It’s also a time when the games are going to move to […] The post Phillies Broadcaster John Kruk Gets Postseason Assignment appeared first on HEAVY.
The science of speed suits: Do they really make you faster?
The suits are designed to reduce 'wake drag', potentially helping save time and energy
Situation analysis of disability-inclusive health systems in the Eastern Mediterranean Region
Analysis in English on Afghanistan and 21 other countries about Health and Protection and Human Rights; published on 28 Sep 2026 by WHO
WHO Situation Report No.3: Health emergencies in the Eastern Mediterranean Region (August 2026)
Situation Report in English on Afghanistan and 11 other countries about Food and Nutrition, Health, Epidemic and more; published on 27 Sep 2026 by WHO
New Jersey Republican Tom Kean Jr. and Democrat Rebecca Bennett clash over war in Iran, tariffs
Tom Kean Jr., the New Jersey Republican congressman whose four-month absence from the House this year went unexplained until he disclosed that he was being treated for depression, clashed with
The Witcher 3 Remastered a 45GB PS5 Patch, Release Times Revealed
An update to current PS5 version
A Dolly Parton tribute, Madonna performs, LISA wins: What to know about the 2026 MTV VMAs
Madonna opened the starry 2026 MTV Video Music Awards and was joined by her recent collaborators Sabrina Carpenter and Charli xcx. LISA won the first award for best pop. Kacey
Madonna opens starry 2026 MTV VMAs, LISA wins first award: What to know about the show
Madonna opened the starry 2026 MTV Video Music Awards. She was joined by her recent collaborators Sabrina Carpenter and Charli xcx. LISA won the first award for best pop. Later
Trump asked China\'s president if he wants to buy US arms, ambassador says
The U.S. ambassador to China says President Donald Trump asked Chinese President Xi Jinping if he wanted to buy weapons from the United States. David Perdue made the statement on
Why rehabilitation cannot be an afterthought in a health emergency: a new WHO toolkit is put to the test
When disaster strikes, saving lives is the priority. But what happens to the people who sustain injuries such as amputations, spinal cord damage, brain injury, or complex fractures if rehabilitation is not part of the response plan from the start? That question shaped a four-day training workshop held in Nadi, Fiji, from 14 to 17 April 2026, where 23 emergency managers, rehabilitation professionals, and partner representatives from 12 countries piloted a new World Health Organization (WHO) toolkit designed to help ministries of health build rehabilitation into their emergency preparedness planning.
WHO recognizes healthy, innovative cities across the Western Pacific Region
Nine Healthy City champions from across the World Health Organization (WHO) Western Pacific Region received special recognition at an awarding ceremony during the 11th Global Conference of the Alliance for Healthy Cities in Sydney, Australia.The WHO Regional Office for the Western Pacific has presented the Healthy Cities Recognition Awards every two years since 2004 to celebrate innovative and impactful city-led initiatives that improve the health and well-being of urban populations.Eight cities received awards for their best practices, and one National Forum received the WHO Regional Director’s Special Award in recognition of its long-standing leadership in advancing the Healthy Cities movement.Awardees were selected through a rigorous evaluation process and recognized for demonstrating measurable, innovative and sustainable approaches to health challenges faced by cities.Remarking on the significance of the awards, Dr Huong Tran, Director of the Division of Health Promotion, Disease Prevention and Control at the Regional Office, said that, “There is no single blueprint for a healthy city. What works in one context may need to be adapted to another. But by sharing our experiences, including what worked, what was challenging, and what we learnt along the way, we can help one another move faster and further.”Award-winning cities and initiativesThis year's awards recognize outstanding city-led initiatives that have demonstrated measurable impact, innovation and sustainability in advancing health initiatives for urban populations.Baguio City (Philippines) – Data for equity: informing action, improving healthDr Donnabel Tubera-Panes, City Epidemiologist – Medical Officer IV of the Health Services Office accepted the award on behalf of Baguio City. Photo credit: Maria BoyadgisBaguio City was recognized for developing a pioneering Livability Index that provides village-level data across all 128 barangays (villages), enabling evidence-based planning and more equitable allocation of resources. By integrating community participation and institutionalizing the index within city planning and budgeting processes, the city has demonstrated how data can drive action to reduce health and social inequities.Eunpyeong-gu (Seoul, Republic of Korea) – Communities living in vulnerable situations: advancing health equity through community engagementVice Mayor Honourable Ahn Hyoung Jun accepted the award on behalf of Eunpyeong-gu. Photo credit: Maria BoyadgisEunpyeong-gu was recognized for its inclusive health equity programme supporting vulnerable populations, including isolated older adults and LGBTQI+ communities. Through peer-led community networks, social cooperatives and inclusive service design, the district has strengthened access to care, promoted social inclusion and advanced community ownership of health initiatives.Madiun City (Indonesia) – Adapting and mitigating climate-related crises: building heat resilience and preventing flood-related health risksMs Yuni Dwi Purwani, Secretary General of the National Forum for Indonesian Healthy Cities/Regencies, accepted the award on behalf of Madiun City. Photo credit: Maria BoyadgisMadiun City was recognized for its SUPERMIE (Sustainable Public Environmental Management Initiative) – a community-based environmental governance model that addresses urban flooding, climate resilience and environmental sustainability. The initiative contributed to reductions in flood-prone areas, greenhouse gas emissions, diarrhoeal disease and dengue fever, while at the same time improving food security through neighbourhood food gardens. The programme has already been replicated in 15 cities and regencies across Indonesia.Macao Special Administrative Region (China) – Protecting communities from tobacco and alcohol-related harms: tackling commercial drivers of riskDr LO Iek Long, Director of the Health Bureau, Macao SAR, China accepted the award on behalf of Macao. Photo credit: Maria BoyadgisMacao SAR was recognized for implementing a comprehensive and integrated approach to tobacco and alcohol control. Through legislation, monitoring systems, enforcement, public awareness campaigns and multisectoral partnerships, the programme has strengthened protection against major risk factors for noncommunicable diseases and established a model that is highly transferable to other urban settings.Phnom Penh Capital City (Cambodia) – Safe, active and health-enabling transport: advancing health and reducing inequities in urban mobilityH.E. Khoung Sreng, Governor of Phnom Penh Capital City accepted the award on behalf of Phnom Penh Capital City. Photo credit: Maria BoyadgisPhnom Penh received the award for its Safe School Zone Project, which combines infrastructure improvements, speed management, enforcement, education and stakeholder engagement to protect children and communities. The initiative has demonstrated measurable reductions in crashes and vehicle speeds while providing a scalable model for safer urban mobility across the country.Quezon City (Philippines) – Transforming food environments: addressing policy, market and urban design drivers of health and nutritionMs Jirah Asa M. Sideco, Chief of the Nutrition Section of the Quezon City Health Department accepted the award on behalf of Quezon City. Photo credit: Maria BoyadgisQuezon City was recognized for its public food procurement policy that promotes healthier diets through government-run institutions and feeding programmes. Supported by strong policy frameworks and monitoring systems, the initiative improves access to nutritious food for vulnerable populations while serving as a benchmark for other local governments.Samarinda City (Indonesia) – Preventing violence and promoting gender equality: transforming urban systems, norms and spaces Mrs Rinda Wahyuni, Chairperson of Samarinda Healthy City Forum accepted the award on behalf of Samarinda City. Photo credit: Maria BoyadgisSamarinda City was recognized for its multisectoral approach to preventing violence and advancing gender equality. Responding to local evidence on violence against women and children, the city has positioned violence prevention as a public health priority, bringing together health services, schools, social welfare institutions, law enforcement, civil society and community leaders to strengthen prevention, reporting, survivor-centred support and legal protection. Through inclusive policies, community engagement and sustainable city financing, Samarinda has developed a locally owned and scalable model for creating safer, more equitable and inclusive urban communities.Singapore – Age-friendly cities: transforming systems to bridge generations for a healthier tomorrowDr Tan Weng Mooi, Director, Integrated Health Promotion, accepted the award on behalf of Singapore. Photo credit: Maria BoyadgisSingapore received recognition for its Healthy Precinct Framework, which translates national healthy ageing priorities into neighbourhood-level action. The initiative integrates preventive care, social support, service coordination and age-friendly environments while actively engaging older persons, caregivers and community organizations. Its expansion across multiple precincts demonstrates its scalability and long-term sustainability.WHO Regional Director’s Special AwardNational Forum for Indonesian Healthy Cities/Regencies (Indonesia)Ms Yuni Dwi Purwani, Secretary General of the National Forum for Indonesian Healthy Cities/Regencies, accepted the award on behalf of the National Forum. Photo credit: Maria BoyadgisThe WHO Regional Director's Special Award was presented to the National Forum for Indonesian Healthy Cities/Regencies (FKKSI) in recognition of its long-standing leadership in advancing the Healthy Cities movement across Indonesia. As a national platform bringing together local governments, communities, academia and civil society, FKKSI has played a critical role in promoting collaboration, capacity-building, knowledge exchange and advocacy. Its efforts have strengthened and institutionalized healthy urban development nationwide and established a model for multisectoral engagement in the Region. Healthy Cities for allThe 2026 Healthy Cities Recognition Awards highlight how cities can lead transformative action on health by addressing climate change, inequity, ageing, nutrition, mobility, social inclusion, violence prevention and the commercial determinants of health. The recognized initiatives demonstrate that local governments, communities and partners can work together to create healthier, safer and more resilient urban environments for everyone. As urban populations continue to grow across the Western Pacific Region, WHO remains committed to supporting cities in advancing health, equity and sustainable development through the Healthy Cities approach and the Alliance for Healthy Cities. ###Note to editorsSince 2004, the WHO Healthy Cities Recognition Awards have provided a platform for cities to share innovative and effective approaches to improving health and well-being. The awards recognize achievements in areas including climate resilience, healthy ageing, health equity, gender equality, tobacco and alcohol control, urban mobility, nutrition and data-driven governance. In 2026, more than 150 submissions were received from cities and local governments across the Western Pacific Region. The titles and affiliations of awardees are presented as they were at the time the photo was taken.______________For more information, or to arrange media interviews, contact: WHO Regional Office for the Western Pacific: wprocom@who.int
Art that serves others: How a Harnett County muralist is making a lasting mark in her community
Van Goat Studios, which has been operating since 2019, has allowed Johnson to express herself and reflect the spirit of local communities through murals. Photo provided by Elyse Johnson.Elyse Johnson of Van Goat Studios in Dunn wants to spread her artistry and make a lasting mark in her community. Van Goat, which has been operating since 2019, has allowed Johnson to express herself through murals and decorating electrical boxes in the urban landscapes of North Carolina. On top of traditional mural painting, Johnson offers what she calls “portable murals,” an option tailor-made for structure owners who do not want to commit to a design for their wall.“A contractor builds a framed piece of wood, and then they can frame the ‘mural’ onto the wood, whether it’s into their building, whether it’s interior or exterior,” Johnson said. The beginnings of Johnson’s journey into establishing Van Goat Studios reflect the teachings she wants artists to take away today: everything is a learning opportunity. When she started Van Goat, she shared it was a joint venture with a business partner. “I mainly did that because I didn’t feel like I was ready to go and do this on my own,” Johnson said. Her business partner eventually dropped out of the project, deciding she wanted to pursue other forms of art. That is when Johnson was thrust into growing her business on her own during and in the aftermath of the COVID-19 pandemic. “I had built up my confidence enough to go out and reach new heights,” she said. “And I was probably one of the few that benefited from COVID.”The moment presented a silver lining for Johnson. One of her first projects was a Farmers Day mural for the town of Coats. “When COVID-19 hit, Coats was not able to hold their annual festival, so they had a little bit of savings. They decided they wanted to do something for their community without getting anyone sick,” Johnson said.From there, word of mouth spread. Now, Johnson has an organic way of approaching projects. “Like a lot of muralists, if I feel inspired by a building, I will just go up and talk to that building owner and tell them a mural is something they should consider,” Johnson said. But above all, Johnson says she wants art to be accessible to everyone. Johnson said she is trying to stick to projects that benefit “the little guys.” “I’m not trying to go for a project in downtown Raleigh to get the eight-foot-tall building,” Johnson said. “I’m not trying to go to those major cities and get those huge buildings for two reasons: one, I don’t want to go that high; two, my passion really lies with the small guys.” But due to financial constraints and the material reality of art commerce, that requires open communication, she added. “I don’t want to just snowball you with this huge price, and then you just shut me down because it wasn’t what you were thinking,” Johnson said. “At the same time, I am an advocate for the arts, so I’m not going to give you a $10,000 mural when you’re only going to pay $5,000.” There is a healthy balance in explaining the artistic process and working with clients and the surrounding community, Johnson said.“Your municipality invested this, and this is why they invested this, and this is how it’s going to help and improve your community,” she noted. “Same thing when I’m talking to a small business. You asked for me to come at you with this that is outside your budget. How do we make this still your same exact goal, but within your budget lines?” Johnson also provides lessons to aspiring artists. She does so with a mission: how do you master the balance between being a great artist and a competent business owner? “We still do art lessons, but I’m also going to give you business scenarios,” she noted.One of the scenarios she has come up with for her students is a T-shirt competition. “The kids have to think about ‘okay, I can’t just draw whatever I want on a T-shirt. I need to think about what colors Miss Elyse likes. What does Miss Elyse’s logo look like? What would Miss Elyse like?’” Johnson said. “So the design needs to be around that kind of concept.” As Johnson looks toward the future of Van Goat Studios, she is thinking of time, longevity and succession. Johnson is a new mom, which she said has shaped how she sees the future of the studio.“I still want my name and my business out there continuing, so that when my daughter is of age and she can be more independent, then I can be out there doing more and more,” Johnson said. “I would love to get a student to pass this on to, or an intern. I would love for this business to be passed on to the next generation and let them go.”
Trump to travel to Ohio to stump for Sen. Jon Husted as the Republican faces competitive challenge
President Donald Trump plans to visit Ohio on Saturday in support of Sen. Jon Husted as the Republican tries to fend off a competitive challenge from Democratic former Sen. Sherrod
Kruk and Kuip: Baseball's legendary Bay Area duo make final call for Giants
San Francisco Giants legendary broadcasters Mike Krukow and Duane Kuiper make their final call together.
Scientists Blasted Water With Light 10 Billion Times Brighter Than Sunlight. It Still Didn't Evaporate Faster.
Illuminating one of recent science's most intriguing mysteries.
Republican senator criticizes White House for taxpayer-funded Trump ads
John Kennedy pushes back against such spending as pro-Trump ‘public service announcements’ air before midterms
AP Top 25: How Channel 2 sports director Zach Klein voted in this week’s poll
The Southeastern Conference has 10 teams in this week’s poll, including both of the top 2.
UK to open new refugee resettlement routes for Afghan women and Palestinians
Exclusive: Move by Shabana Mahmood comes after closure of Afghan scheme last year but experts say numbers too small to deter Channel crossings
Can Bionic Reading really help you read faster? Scientists put it to the test
Bionic Reading is a method of bolding certain letters in words that is purported to facilitate reading speed and comprehension. The idea is that guiding the eyes to focus on highlighted initial letters ...
Facing up to the threat that Reform poses to our democracy
Letters: Readers respond to an article by John Harris in which he urges Labour to offer hope and change
Changing UK benefits for young people a ‘moral crusade’, says minister
Pat McFadden urges Labour MPs to back overhauls, amid signs party looking to cut payments for some 16- to 24-year-olds
Witcher Dev Reveals Why CD Projekt Red Doesn't Do Crossovers In Its Own Games
A Geralt-inspired skin is coming to Diablo 4, but don't expect Diablo characters in The Witcher 3 Remastered
Nor'easter update: Shore battered by wind, floods for second day
A powerful nor'easter is pounding the Jersey Shore with high winds and floods for a second straight day.
Sunday Puzzle: So-so
NPR's Ayesha Rascoe and WYPR listener Katherine Jakuta of Baltimore, Maryland play the puzzle with Weekend Edition puzzle master Will Shortz.
Bad language: profane Trump brings presidential swearing out into open
President has let rip with swearwords in recent months, redefining norms about acceptable language in public office
Glucosamine, a popular joint supplement, linked to faster Alzheimer’s progression
A large health-record analysis found that glucosamine use was associated with a 25% higher likelihood of mild cognitive impairment progressing to dementia. Lab experiments suggest the popular joint supplement may intensify an abnormal sugar-tagging process in the Alzheimer’s brain, although researchers say clinical trials are needed to determine whether it actually causes harm.
Glucosamine, a popular joint supplement, linked to faster Alzheimer’s progression
A large health-record analysis found that glucosamine use was associated with a 25% higher likelihood of mild cognitive impairment progressing to dementia. Lab experiments suggest the popular joint supplement may intensify an abnormal sugar-tagging process in the Alzheimer’s brain, although researchers say clinical trials are needed to determine whether it actually causes harm.
Labour is nostalgic for two-party politics. That cosy, simple time is over
Our fragmented political model will endure for the foreseeable future – and Reform will benefit from it until Burnham learns that cooperation is key, says Guardian columnist John Harris
Burnham’s plan for a radical reset collides with economic reality
Surging energy bills, higher borrowing costs and rising inflation have left the PM and his chancellor in a fiscal bind
Broncos offense knows it needs to start faster
Denver’s offense has struggled to find its rhythm early, and the Broncos know they need to be better from the start.
‘It’s problematic’: Concern as Vogue World event sponsored by ‘skinny jabs’ maker
Partnership between Mounjaro maker Eli Lilly and fashion giant, suggests thinness is an aspiration says critics
‘It’s problematic’: Concern as Vogue World event sponsored by ‘skinny jabs’ maker
Partnership between Mounjaro maker Eli Lilly and fashion giant, suggests thinness is an aspiration says critics
In a mysterious reversal, Earth’s atmosphere has gotten less dusty
The amount of dust in the atmosphere has fallen over the last 20 years, recent research shows. Could that explain why the planet has been warming faster than expected?
Mercury is shrinking faster than anyone thought
Wrinkles on the surface are clues as to the planet’s previous size
Could Republicans flip New Hampshire Senate seat? Sununu's got a shot
Republicans, some national forecasters and pundits believe that the GOP has a chance to flip the state’s U.S. Senate seat.
London’s investment bankers and lawyers make more than £1bn in takeover frenzy
Bumper fees paid in the year’s mergers and acquisitions spark anger over high City pay during cost of living crisis
See top photos from Nashville SC's match against Toronto FC
See photos from Nashville SC's Eastern Conference matchup against Toronto FC at Geodis Park on Sept. 26.
Diamondbacks bullpen game disaster may cost them a playoff spot
The Diamondbacks snapped a six-game winning streak by losing a bullpen game that involved perplexing twists, turns and decisions.
KREM 2 News
Welcome to the YouTube channel for KREM 2 News. KREM 2 News is the local CBS-affiliate news station covering Spokane, Eastern Washington and North Idaho. Subscribe for the latest news, weather, features and sports in the Inland Northwest. For the latest news, visit www.krem.com.
Two senior FBI agents ousted over investigation into alleged harassing calls to wife of Trump adviser Stephen Miller
Two veteran FBI agents overseeing counterterrorism operations in the nation’s capital have been removed from their jobs and reassigned over the handling of an investigation involving Katie Miller, the conservative podcaster and wife of senior White House adviser Stephen Miller, according to two people familiar with the move.
UCLA receives $75 million in NSF grants for quantum technology
Two UCLA quantum computing institutes received grants from the National Science Foundation worth a combined $75 million Aug. 25. The institutes – Fault-Tolerant Quantum Systems, Architectures and Applications and Challenge Institute for Quantum Computation – aim to advance quantum technologies, which function faster than classical computers or standard digital devices.
Can Giannis Antetokounmpo Snap a Miami Heat Superstar Trend?
History shows the Miami Heat's blockbuster acquisitions often face first-year hurdles. Now, the Greek Freak aims to defy tradition and navigate a loaded Eastern Conference to secure an immediate title.
Nor’easter knocks out power to 19K homes, businesses in Hudson Valley
As a nor’easter continues to bear down on New York and New England, electricity crews are working to restore power to thousands of customers.
Boston College Comes Up Short, 21-14, to Virginia Tech
On Saturday afternoon, Boston College lost 21-14 to Virginia Tech. The storyline on everyone’s mind heading into this contest was the weather. With a nor’easter rolling into town on Saturday morning, the game was played in constant rain and gusty wind. The conditions drilled both teams, especially in the first half. We did not see […]
Ohio State's Jeremiah Smith Delivers Heisman-Worthy Masterpiece vs. Illinois
Ohio State wide receiver Jeremiah Smith put together a historic, record-setting game in the Buckeyes' win over Illinois.
OU-Georgia: Live updates, TV details
Availability: The final Southeastern Conference gameday availability report dropped ahead of kickoff with junior defensive lineman David Stone listed as a gametime decision and senior linebacker Kip Lewis set to
Belfast court injuncts decision to allow Orange Order march down Garvaghy Road
Andy Burnham calls for calm as fears of unrest grow after request for countermarch in mainly nationalist area
‘Charming and disarming’ … how Meta’s technology-packed Muse harnesses the power of cuteness
The tech giant has launched a cute ‘little guy’ that can answer emails, book travel or do your weekly food shop
Just 4 Minutes a Day: The Surprising Habit Transforming Health After 65 - Futura-Sciences
Why Short Workouts Might Be a Big Deal Starting long or intense workout regimens puts off a lot of people—no surprise there. Yet, muscle strength and balance are crucial for maintaining independence as we age, and unfortunately, these abilities decline faster after age 65. With this in mind, researchers at...
‘I can deliver’: Burnham pledges radical change on eve of Labour conference
Exclusive: UK prime minister says delivering fiscal stability would be ‘crucial’ to be able to fix bigger problems
Texts link Justin Baldoni’s crisis PR pro to 'smear' sites, complaint alleges
Top Hollywood publicist Melissa Nathan faces allegations of playing a key role in running 'smear' sites for embattled celebrities amid the Justin Baldoni legal saga. In a deposition, Nathan denied she was the mastermind behind the now-defunct stephaniejonesleaks.com.
The Witcher 3 Remastered Download Size, Global Release Times and Review Embargo Lift Dates Revealed
In case you missed the big announcement at gamescom last month, CD Projekt RED is set to unleash The Witcher 3: Wild Hunt Remastered this coming week, and it'll be…
Asteroid Bennu may have formed much closer to the Sun than scientists thought
Returned asteroid grains link Bennu, Ryugu and CI meteorites to a mixed dust reservoir shaped by ice and the young Jupiter.
Airlines waive change fees as nor'easter hits Northeast
Over 88,000 customers in the region had lost power as of Saturday morning.
Pennsylvania measles outbreak spreads, with 55 new cases reported since Wednesday
173 people hospitalized and four deaths in state so far, with less than 1% of those infected having been vaccinated
Germany coach Klopp support nation's plans to host Olympics
Germany coach Jürgen Klopp showed his support for the nation's plans to host Olympic Games with an emotional anecdote. "All my memories of sports actually begin with the Olympic Games," Klopp told broadcasters ARD.
Heads of OpenAI and Anthropic called to face Senate inquiry after rogue agent incidents
Sam Altman and Dario Amodei have been invited to appear before the Greens-led inquiry into AI and datacentres
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. [1] Intel, “Intel Tech Tour 2025 Panther Lake recap,” Doc. 866361, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/866361/ITT_2025_Panther_Lake_Recap1.pdf [2] Intel, “Core Ultra processors Series 3 datasheet, volume 1,” Doc. 872188-001, Jan. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/872188/872188-001.pdf [3] N. Horiguchi and E. Beyne, “Backside power delivery: How to power chips from the backside,” imec Reading Room, Nov. 25, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/how-power-chips-backside [4] W. Hafez et al., “Intel PowerVia technology: Backside power delivery for high density and high-performance computing,” in Proc. IEEE Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2023, pp. 1–2, doi: 10.23919/vlsitechnologyandcir57934.2023.10185208. [5] K. Fischer et al., “Intel 18A platform technology featuring RibbonFET (GAA) and PowerVia for advanced high-performance computing,” in Proc. Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2025, pp. 1–3, doi: 10.23919/vlsitechnologyandcir65189.2025.11075006. [6] K.-F. Cheng, C.-L. Teng, H.-Y. Huang, and H.-C. Chen, “Metal oxide composite as etch stop layer,” U.S. Patent 12 176 247 B2, Dec. 24, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12176247B2/en [7] S. W. King, “Dielectric barrier, etch stop, and metal capping materials for state of the art and beyond metal interconnects,” ECS J. Solid State Sci. Technol., vol. 4, no. 1, pp. N3029–N3047, 2015, doi: 10.1149/2.0051501jss. [8] A. V. Mule’, D. J. Towner, D. Seghete, C. R. Ryder, and A. A. Gonzalez, “Multi-layer etch stop layers for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20220102343 A1, Mar. 31, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20220102343A1/en [9] C.-C. Wang and J. H. Wang, “Interconnect structure with dielectric cap layer and etch stop layer stack,” U.S. Patent Appl. 20230253247 A1, Aug. 10, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20230253247A1/en [10] Y. J. Wu, K.-F. Cheng, C.-C. Lee, H.-K. Chang, and H.-Y. Huang, “Etch stop layer for interconnect structures,” U.S. Patent Appl. 20240332070 A1, Oct. 3, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240332070A1/en [11] M. G. Rainville, N. Shankar, K. S. Reddy, and D. M. Hausmann, “Deposition of aluminum oxide etch stop layers,” U.S. Patent Appl. 20180197770 A1, Jul. 12, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20180197770 [12] J. S. Leib et al., “Conductive lines having molybdenum liner and tungsten fill for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20240429126 A1, Dec. 26, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20240429126 [13] M. Naik, “Cobalt enables power and performance scaling at single-digit logic nodes,” Applied Materials, Dec. 17, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://www.appliedmaterials.com/us/en/blog/blog-posts/cobalt-enables-power-and-performance-scaling-at-single-digit-logic-nodes.html [14] Lam Research, “Breaking through AI’s invisible barrier with molybdenum,” Lam Research Newsroom, May 6, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://newsroom.lamresearch.com/molybdenum-metallization-ai-revolution [15] P. Yashar, G. Malyavanatham, and H. Vijwani, “Integrated circuit interconnect structures with niobium barrier materials,” U.S. Patent Appl. 20240112951 A1, Apr. 4, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240112951A1/en [16] Applied Materials, “Applied Materials unveils chip wiring innovations for more energy-efficient computing,” Applied Materials Investor Relations, Jul. 8, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://ir.appliedmaterials.com/news-releases/news-release-details/applied-materials-unveils-chip-wiring-innovations-more-energy [17] Samsung, “Samsung showcases AI-era vision and latest foundry technologies at SFF 2024,” Samsung Semiconductor, Jun. 13, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://semiconductor.samsung.com/news-events/news/samsung-showcases-ai-era-vision-and-latest-foundry-technologies-at-sff-2024/ [18] C. W. Yeung et al., “Channel geometry impact and narrow sheet effect of stacked nanosheet,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2018, pp. 28.6.1–28.6.4, doi: 10.1109/iedm.2018.8614608. [19] S. Mochizuki et al., “Evaluation of (110) versus (001) channel orientation for improved nFET/pFET device performance trade-off in gate-all-around nanosheet technology,” in Proc. Int. Electron Devices Meeting (IEDM), Dec. 2023, pp. 1–4, doi: 10.1109/iedm45741.2023.10413854. [20] D. G. Ouellette et al., “Fabrication of gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer,” U.S. Patent 12 051 698 B2, Jul. 30, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12051698B2/en [21] imec, “Advancing the CFET-based device roadmap with novel integration modules and standard-cell architectures,” imec, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/advancing-cfet-based-device-roadmap-novel-integration-modules-and-standard-cell [22] A. Reznicek, X. Miao, C. Lee, and J. Zhang, “Wrap around contact for nanosheet source drain epitaxy,” U.S. Patent 11 302 813 B2, Apr. 12, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US11302813B2/en [23] J. A. Kittl, J. G. Hong, D. R. Palle, and M. S. Rodder, “Methods for varied strain on nano-scale field effect transistor devices,” U.S. Patent 9 978 833 B2, May 22, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9978833B2/en [24] S. Gandikota et al., “Method of reducing metal gate resistance for next generation NMOS device application,” Int. Patent Appl. WO 2024/137272 A1, Jun. 27, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/WO2024137272A1/en [25] J. Zhang et al., “Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2019, pp. 11.6.1–11.6.4, doi: 10.1109/iedm19573.2019.8993490. [26] C. Yoo, J. Chang, Y. Seon, H. Kim, and J. Jeon, “Analysis of self-heating effects in multi-nanosheet FET considering bottom isolation and package options,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1524–1531, Mar. 2022, doi: 10.1109/ted.2022.3141327. [27] S. S. Pradhan, D. B. Bergstrom, J.-S. Chun, and J. Chiu, “Tungsten gates for non-planar transistors,” European Patent Appl. EP 3 506 367 A1, Jul. 3, 2019. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/EP3506367A1/en [28] L. Schloss and X. Ba, “Tungsten films having low fluorine content,” U.S. Patent 9 754 824 B2, Sep. 5, 2017. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9754824B2/en [29] Intel Foundry, “Accelerating AI and HPC with advanced process and packaging technologies,” Doc. 367370-001US, Jun. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf [30] M. Lofrano, X. Chang, H. Oprins, and Z. Tokei, “Mitigating the thermal bottleneck in advanced interconnects,” imec, Sep. 28, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/mitigating-thermal-bottleneck-advanced-interconnects [31] S. Bair, “Intel at ISSCC 2025: Navid Shahriari invited talk, eight papers, forums, panelist & product details,” Intel Community, Feb. 19, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://community.intel.com/t5/Blogs/Tech-Innovation/Edge-5G/Intel-at-ISSCC-2025-Navid-Shahriari-Invited-Talk-Eight-Papers/post/1667592 [32] D. Chandra, E. Potladhurthi, D. R. S. Reddy, and K. S. Rengarajan, “Tunable negative bitline write assist and boost attenuation circuit,” U.S. Patent Appl. 20160203857 A1, Jul. 14, 2016. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20160203857A1/en [33] Synopsys, “Advantages of firmware-based training in high-speed DDR IP,” Synopsys IP Technical Bulletin. Accessed: Sep. 14, 2026. [Online]. Available: https://www.synopsys.com/articles/firmware-based-training-ddr-ip.html [34] N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “CACTI 6.0: A tool to understand large caches,” Hewlett-Packard Laboratories, 2009. Accessed: Sep. 14, 2026. [Online]. Available: https://users.cs.utah.edu/~rajeev/cacti6/cacti6-tr.pdf [35] Intel, “Intel Tech Tour 2024 Lunar Lake AI hardware accelerators,” Doc. 824436, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/824436/2024_Intel_Tech%20Tour%20TW_Lunar%20Lake%20AI%20Hardware%20Accelerators.pdf [36] Y.-H. Chen, J. Emer, and V. Sze, “Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks,” in Proc. 43rd ACM/IEEE Annu. Int. Symp. Comput. Archit. (ISCA), Jun. 2016, pp. 367–379, doi: 10.1109/isca.2016.40. [37] Intel, “Introduction to the Xe-HPG architecture,” Doc. 758306, Nov. 4, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/developer/articles/technical/introduction-to-the-xe-hpg-architecture.html [38] Intel, “Core Ultra processors Series 3 for the edge,” Doc. 855291. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/855291/Intel%C2%AE%20Core%E2%84%A2%20Ultra%20Processors%20Series%203%20for%20Edge%20Overview_2.pdf [39] Intel Foundry, “Foveros technology brief,” Doc. 366411-001US, Feb. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-07/foveros-25d-product-brief.pdf [40] D. Das Sharma, “UCIe: Building an open chiplet ecosystem,” UCIe Consortium, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.uciexpress.org/_files/ugd/0c1418_c5970a68ab214ffc97fab16d11581449.pdf [41] Intel, “Intel launches Intel Core Series 3 processors,” Intel Newsroom, Apr. 16, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-launches-intel-core-series-3-processors-changing-the-game-for-everyday-computing.html [42] Intel, “Core Series 3 launch press deck,” Apr. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://download.intel.com/newsroom/2026/Intel-Core-Series-3/Intel-Core-Series-3-Launch-Press-Deck.pdf [43] Intel, “Intel outlines architectures for agentic AI at Hot Chips 2026,” Intel Newsroom, Aug. 24, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-outlines-architectures-for-agentic-ai-at-hot-chips-2026.html [44] Intel, “Intel accelerates process and packaging innovations,” Intel Investor Relations, Jul. 26, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-21-224438/d199788dex991.htm [45] Intel, “Intel reports third-quarter 2021 financial results,” Intel Investor Relations, Oct. 21, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/1505/intel-reports-third-quarter-2021-financial-results [46] Intel, “3rd generation Intel Core processors bring exciting new experiences and fun to the PC,” Intel Investor Relations, Apr. 23, 2012. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/577/3rd-generation-intel-core-processors-bring-exciting
Can a nuclear bomb really save Earth? Scientists are testing the unthinkable - Futura-Sciences
A Nuclear Bomb in Space: Not Science Fiction Anymore Chinese researchers have just published a remarkable study outlining a radical plan to shield Earth from a giant asteroid: burying a nuclear bomb right into the cosmic boulder. We’re not talking movie magic here—it’s physics, simulations, and cold, hard calculations. The...
Over 70% of US Coastal Areas Are Sinking Faster Than 1 Millimeter a Year
Action is needed now.
Thomas Jefferson letter goes on the market – containing a prescient warning for Trump today
Third US president wrote in 1787 about importance of peace, paying off debt and supporting agriculture
Eastern Conference Collision | Presented by Atrium Health
The official website of Charlotte Football Club of Major League Soccer. Get the latest news, tickets, offers, player updates and more.
Looking back on the \'60s origins of Spider-Man in advance of the 1,000th issue [Unscripted column]
In the fall of 1962, a fantastical story was released to the general public that is still being told, uninterrupted, to this day.
Children\'s artwork to be exhibited, sold in \'Peace Kids\' show to raise funds for nonprofits
At the eighth annual Peace Kids to the Rescue Art Show & Silent Auction, 72 works by children ages 3-18 will fill the third floor of Lancaster’s Ware Center for
Liverpool rehire Julian Ward as sporting director to replace Richard Hughes
Liverpool have appointed Julian Ward as their sporting director for a second time following the departure of Richard Hughes to Al-Hilal
Lula bans fixed-odds sports betting a week before Brazilian elections
President’s ‘hard, drastic and necessary measure’, likely to attract widespread public support, polls suggest
From Sense and Sensibility to Kill Jackie: your complete entertainment guide to the week ahead
Daisy Edgar-Jones dons the bonnet in Georgia Oakley’s take on the Jane Austen classic, and Catherine Zeta-Jones battles assassins in a madcap action caper
The Cask of Amontillado
Edgar Allen Poe was a master of the horror genre, and one of my favorite short stories of his is “The Cask of Amontillado.” The story, which takes place in
Tri-State Area residents, business owners brace for nor'easter
Reception supports EPHC health care scholarship
The Eastern Plumas Health Care Foundation invites the community to gather for an afternoon reception on Saturday, Nov. 14, featuring locally inspired hors
REM sleep paradox: Dreaming may drain the brain’s energy even as fuel supply rises
Scientists discovered a surprising energy paradox in the brain during REM sleep, the stage most closely associated with dreaming. Blood supply to the brain begins increasing even before REM starts, but neurons’ immediately available energy, measured as ATP, then drops. The finding suggests that dreaming may require such intense internal processing that neurons consume energy faster than it can be replenished.
White House claims pro-Trump ad it paid Fox to air was ‘public service announcement’
Some Democrats say taxpayer-funded ad could be illegal government propaganda aimed at influencing voters
After Much Political Ado, Ed Sheeran’s Boston Concerts Are Canceled for Weather
The cancellations come after the Gillette Stadium owner pressured Mr. Sheeran to remove an act who made pro-Palestine statements.
Polls show a snapshot of Minnesota's political landscape
All Things Considered host Clay Masters and the MPR News politics team break down a week in Minnesota politics with a recap of the latest polling data.
100 days after Boyle Heights warehouse fire, health concerns persist in surrounding neighborhood
One hundred days after the Lineage warehouse fire in Boyle Heights, health care providers say residents continue to experience physical and mental health effects linked to the disaster.
Dengue fever researcher talks Florida outbreak
Authorities in Florida have declared local states of emergency following an outbreak of dengue fever that has so far resulted in one death.
New Jersey’s lieutenant governor resigns after sexual harassment and ethics complaints
New Jersey’s Democratic lieutenant governor has resigned after the governor demanded he step down over allegations of inappropriate behavior with women. Gov. Mikie Sherrill had given Lt. Gov. Dale Caldwell
Photos: Fall semester, soap carving and business built by grads
Happy Friday, Huskies! This week, students in Oakland held a new kind of student government election. Over in Boston, dive inside the Soap Carving Club’s growing popularity. And, graduates share the businesses they build through entreprenuership.