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Velocity Raises $38 Million as Stablecoins Reshape Mainstream Business Finance
Velocity raised $38 million in a Series A funding round to expand its stablecoin payments and treasury platform designed for global enterprises, according
MPs say death threats a daily reality in ‘increasing climate of abuse’
As Ann Widdecombe’s death raises concerns over security, politicians reveal extent of problem
Flex Raises $70 Million To Put Business Banking On Stablecoin Rails
Invisible stablecoin rails are making cross-border banking faster for business owners. Flex has raised a $70 million Series B1 to capitalize on the shift.
Sotheby’s Big T. Rex Auction Raises Concerns Hype and Wealth Are Upending Science
Private buyers are increasingly outbidding museums for fossils. That’s making it difficult—or even impossible—for researchers to improve our understanding of the past.
Report raises questions over Attorney General Ken Paxton’s voter registration
A new investigation scrutinizes whether the Republican Senate nominee may have violated the same voting laws his office has aggressively enforced.
Soccer, not just American football, may affect long-term brain health, study suggests
As the World Cup nears its final, a new study raises questions about whether long-term soccer head impacts could affect brain health.
Exclusive: Corner Health raises $25 million to turn nurse practitioners into entrepreneurs
Women dominate NP roles—and can double their salaries in 27 states where they're permitted to practice independently.
Bosses credit AI instead of employees, delaying promotions, raises
Bosses are crediting AI with work that human employees actually did. People said the mistaken attribution is delaying promotions and cutting raises.
Summer Games Done Quick 2026 raises another $2.4 million for Doctors Without Borders
The annual speedrunning marathon, held in Minneapolis this week, welcomed around 2500 in-person attendees, as well as thousands via its livestreams.
Brandon Graham praises Jalen Hurts, Vic Fangio’s Eagles defense
Brandon Graham joined NFL Network's Good Morning Football and offered some early expectations of where the Eagles are headed.
Steelers Legend Hines Ward's Max Iheanachor Endorsement Raises Expectations
One of the Pittsburgh Steelers' biggest long-term projects is first-round pick Max Iheanachor. The athletic offensive tackle possesses tremendous upside, but much of that potential stems from the fact that he only began playing football a few years ago. A national analyst and a Steelers legend both believe that potential is real, offering strong endorsements of Iheanachor's future.
GoFundMe raises over $400K for family of slain business owner Lorenzo Salgado Araujo
“He was the kind of man who showed up: for his family, for his friends, for his neighbors, and on every job he ever took.”
GoFundMe raises over $400K for family of slain business owner Lorenzo Salgado Araujo
“He was the kind of man who showed up: for his family, for his friends, for his neighbors, and on every job he ever took.”
NC State Health Plan raises premiums, offers new tiered benefits that could help members cut costs
The N.C. State Health Plan's Board of Trustees voted Friday morning to raise premiums for many of its 770,000 members.
NC budget raises sports-betting tax, adds prediction markets
New NC budget raises sports-betting taxes, redirects revenue to public universities, and creates a new tax on prediction markets.
Melissa Gilbert names the most progressive episode of original ‘Little House on the Prairie’
Melissa Gilbert is looking back on the original ‘Little House on the Prairie’ ahead of the new Netflix series, and singing the praises of this progressive 1977 episode: ‘I don’t think we get more woke than that.’
TN Politics: Final MSCS forensic audit raises political concerns
The complete report points to more than $100 million in "waste, fraud and abuse." Who fixes the problem is still being debated.
Senegal’s Political Rupture Raises Risk of Debt Reprofile, Says Citibank
Senegal’s Political Rupture Raises Risk of Debt Reprofile, Says Citibank
EA SPORTS™ College Football 27 Launches Worldwide, Bringing New Era of College Football to Life
Do it For U with 138 Ways to Play in Dynasty Mode, Experience NIL and Build Your Legacy In Road to Glory Electronic Arts Inc. (NASDAQ: EA) today launched EA SPORTS™ College Football 27 worldwide on PlayStation®5, Xbox Series X|S and, for the first time ever, PC and mobile. Following the record-breaking return of the franchise, College Football 27 raises the bar once again, delivering the most authentic college football experience yet. College Football 27 captures real world elements that impact gameday like never before. College Football 27 is the definitive modern college football experience. Every major change happening in the sport — from NIL and coaching movement to recruiting, player development and game day — is now reflected in the game at unprecedented scale. Built around the current college football landscape, College Football 27 introduces the biggest changes to Dynasty Mode since the game's introduction, including all-new dynamic weather, expanded Road to Glory positions
In shift, Trump praises Zelensky, will let Ukraine build Patriot missiles
It was a dramatic departure from Trump’s more acerbic tone toward Ukrainian President Volodymyr Zelensky, whom he once derided as ungrateful.
Pearl Health Raises $110 Million to Expand Its AI Platform Helping Providers Deliver Better Outcomes at Lower Cost for Medicare Patients
/PRNewswire/ -- Pearl Health, a healthcare technology company helping manage risk and deliver better care to Medicare patients, today announced a $110 million...
Are glucose monitors a good thing for 2-year-olds? Experts look at risks, benefits
The newly approved over-the-counter CGM offers a new approach to tackling childhood obesity but also raises a host of questions.
Is AMC Entertainment Holdings (AMC) Still Undervalued As It Raises Equity To Cut Debt?
AMC Entertainment Holdings (AMC) has drawn fresh attention after raising about US$200 million through a registered direct common stock offering, with plans to redeem its 6.125% Senior Subordinated Notes due 2027. See our latest analysis for AMC Entertainment Holdings. At a share price of US$1.72, AMC Entertainment Holdings has seen pressure in the very short term, with the 7 day share price return down 9.47%. However, a 90 day share price return of 28.36% and a year to date gain of 6.83%...
City Council poised to approve big pay raises
Under proposed legislation, the city’s elected officials would get an 18.2% pay increase.
Falcons Recap: Tom Brady's admission, ESPN praises Terrell brothers
Tom Brady says World Cup win tops 28-3, ESPN praises Terrell brothers in new Falcons Recap
Orbit Fab hires new CEO and raises funding to support satellite refueling business
With a new chief executive and funding round, satellite refueling company Orbit Fab hopes to make the transition from technology development to operations.
Trump praises Turkish leader, stops short of approving fighter-jet sale
President Donald Trump heaped praise on Turkey's president but stopped short of publicly approving the sale of F-35 fighter jets, which many in Congress oppose.
Cancer Health: HIV raises hepatitis C liver disease risk in women more than men
Women with HIV and HCV face higher odds of cirrhosis and liver decompensation but not liver cancer.
Universal Health Services (UHS) Stock May Trade At A Discount On Medicare Payment News
Universal Health Services stock has rebounded in the short term but is still down sharply year to date, which sits alongside valuation checks that currently paint the shares as looking cheap rather than stretched. After falling 28% year to date, Universal Health Services now raises the question of whether the recent bounce is simply a recovery from depressed levels or a sign that value investors are stepping back in. Expectations for solid earnings and ongoing support from Medicare payments...
Could We Have Been Wrong About Fish Oil and Brain Health? New Study Raises Major Questions
Fish oil supplements delivered omega-3s to the brain, but a new study found that was not enough to improve cognitive health in older adults at risk for Alzheimer’s.
This toad exists only in Canada—and scientists have finally discovered why
Scientists have identified something that may be even more uniquely Canadian than the beaver or moose: a genetically distinct western toad population found only in Canada. The discovery, made by researchers from the University of Ottawa, points to a rare and previously unrecognized group of toads living in the Canadian Rockies and raises fresh questions about conservation, biodiversity, and how much wildlife still remains to be fully understood.
Pickleball tournament raises over $40,000 for community health center
Through three days of pickleball, Elevated Community Health’s 2nd annual Elevated Paddle Battle tournament raised over $40,000. The tournament, which ran from June 26-28 in Breckenridge’s Carter Park, featured 100 players from 12 states, all...
Trump's massive July 4 firework show raises health alarms
An "unforgettable" tribute to America, or a health hazard that will terrorize animals and pollute the environment?
Premier Lacrosse League raises $100 million as sport gears up for ‘biggest moment’ in its history
Another big valuation moment for an up-and-coming sports league.
NI health: Audit Office raises concerns over 'deteriorating' health buildings
A report by the Auditor General finds only 40% of health facilities are in an acceptable condition.
LeBron James praises Balogun after 'Silencer' celebration
Basketball superstar LeBron James congratulated Folarin Balogun on scoring for the United States in their World Cup victory on Wednesday after the striker emulated his trademark "Silencer" celebration."THE (Silencer) HAS (Arrived) at the World Cup!"
Apple to launch 5 new iPhone models to gain market share amid memory crunch
Company raises production target for first foldable phone to about 10 million units
Great-grandson of Wong Kim Ark praises Supreme Court ruling affirming birthright citizenship
The great-grandson of Wong Kim Ark, the Chinese American at the center of the U.S. Supreme Court case that established the constitutional guarantee of birthright citizenship, called Tuesday’s ruling a victory for all Americans, saying it reaffirmed that precedent.
South Coast Business & Technology Awards Raises More Than $200,000 for Scholarship Foundation
William Wang, Mission Wealth, and UCSB Dept. of Technology Management among the honorees
Penn State's Rocco Becht praises QB2 Alex Manske
Penn State quarterback Alex Manske faces a critical path forward after an injury sidelined his spring development.
What 124 Future Business Leaders Really Think About AI and Work
Insights from 124 career assessments written by UMD-Smith graduate students show 98% expect artificial intelligence to transform, not eliminate, their careers. The analysis also found AI raises performance expectations while increasing demand for strategic thinking, AI literacy, ethical judgment and critical evaluation of AI-generated work.
Jodie Sweetin praises “Better Call Saul ”actor cast as dad in “Full House ”pilot, but Bob Saget was always 'first choice'
Saget was engaged to cohost CBS' "The Morning Program" when he got the call for "Full House," which led to his absence in the original pilot.
Jodie Sweetin praises 'Better Call Saul' actor first cast as 'Full House' dad, but Bob Saget was No. 1 choice
Bob Saget nearly missed the chance to play Danny Tanner on 'Full House,' and though he was casting's 'first choice,' Jodie Sweetin says this 'Better Call Saul' star was 'very sweet' in the original pilot.
Andy Burnham’s meteoric rise tells us much about how politics and power are changing
The former may of Greater Manchester’s rise raises questions about the changing dynamics of political parties and leadership in an accelerated political climate.
This Week’s Small Business Tech News: Apple Significantly Raises Their Prices
AI is reshaping small business IT, customer service and marketing. Learn why Microsoft agents, Apple price hikes and AI influencers matter to your business.
San Antonio Pride festival celebrates LGBTQ+ community, raises money for local nonprofits
Thousands of people were expected at Crockett Park on Saturday for the Pride Bigger Than Texas Festival, an eight-hour celebration of LGBTQ+ history, resilience and community support.
Morgan Stanley Raises PT on International Business Machines (IBM) Stock
International Business Machines Corporation (NYSE:IBM) is one of the Best Cloud Computing Stocks to Buy According to Hedge Funds. On June 23, Morgan Stanley lifted its price objective on the company’s stock to $267 from $225, and maintained an “Equal Weight” rating on the shares. As per the analyst, Dell and HPE earnings demonstrate that the enterprise server demand […]
Nigel Farage’s anti-WHO campaign moves to US with allies added to board
Relocation of Action on World Health raises questions over why Reform UK leader is involved in a US pressure group
Nigel Farage’s anti-WHO campaign moves to US with allies added to board
Relocation of Action on World Health raises questions over why Reform UK leader is involved in a US pressure group
New iPhone 18 specs report raises big question of iOS 27 limitations
Apple’s base model iPhone 18 might not get as much RAM as expected—raising questions about support for iOS 27’s most demanding features.
Supreme Court rules in weedkiller cancer case
Dems want to unmask Eli Lilly's obesity drug user, a new genome-editing tool raises ethics questions, and more health news
It's Xbox's turn (again), as console prices keep going up
Microsoft announced a price hike for the Xbox Series consoles today, the third in little over a year. Effective August 1, the Xbox Series S, which launched in 2020 for $300, will cost $500 in the U.S. The Xbox Series X, which launched in 2020 at $500, will go for $800. This follows a round of PlayStation 5 price increases from Sony this spring, and a slow-motion increase for Nintendo’s Switch 2, which will kick in in the U.S. in September. (Mind you, there were also eight video game industry price hikes in six months of 2025). The chart up top shows the sudden ascent of console prices over the past year, a sudden surge in an already unusual hardware generation. Prices had been flat for years, now “up” is the new “flat.” Game console prices used to go down across the length of a console generation, but not this time around. Microsoft’s explanation for the new price hike today: We hoped another price increase would not be necessary, and we have spent the last several months working with suppliers on options. Unfortunately, console storage and memory prices have increased by more than 2.5x and we expect another doubling by the fall of 2027. The entire consumer electronics industry is struggling with the current components crisis, but the effects are particularly hard on consoles. Unlike phones, computers, speakers, and other consumer devices, consoles are typically not sold at a profit, but instead for less than they cost to make. This is an issue well beyond game consoles. Apple announced price hikes on its computers and tablets today as well. Game File is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe Item 2: Brutal Bungie cuts Bungie laid off “most” of its Destiny development team and some developers who worked on Marathon, the newest game from the struggling Sony-owned studio. A WARN notice issued by Sony to Washington State, where Bungie is based, tallied cuts impacting 292 workers, effective next month. That’s strictly for Bungie/Sony jobs in Washington and wouldn’t account for any elsewhere. The video I clipped below shows the redacted list of Bungie cuts filed to Washington State officials. As you’ll see, I had to scroll for a while… In a note emailed to PlayStation workers and published online, PlayStation game studios chief Hermen Hulst offered the following explanation for these latest cuts at Bungie: This is painful news, especially for talented colleagues whose roles have been eliminated. This decision was made only after extensive discussion and careful consideration, and I want to provide some context on how we arrived here. Over the past several months, together with Bungie leadership, we reviewed the studio’s long-term direction, development priorities, resource needs, and role within our broader portfolio strategy. We explored multiple alternatives before concluding that a reduction was necessary to align the studio’s resources with its current priorities and long-term goals. In 2022, Sony bought Bungie for $3.7 billion. The studio’s marquee game, the multiplayer live service shooter Destiny 2 was losing popularity at the time. Its next game Marathon, released earlier this year, has been well-reviewed but had a slow start. Bungie is renowned for making great shooter games, and Destiny fans have mourned the wind-down of Destiny 2. They’ve also expressed bewilderment over reports that Destiny 3 is not, per Bloomberg, immediately in the cards.
Dems put on blast over poll that shows record-low patriotism in US: 'Tear our society apart'
Rep. Harriet Hageman raises alarm over Gallup poll showing just 17% of Americans were "very proud" of their country, a record low in 25 years.
Apple raises Mac and iPad prices by as much as 25%
Apple CEO Tim Cook had earlier warned of price increases due to the memory chip shortage.
Europe's heatwave shifts east as as France raises health alert to highest level
Temperatures in Germany could hit 40C in some areas while French officials say deaths linked to the heat are being seen among young people.
Exclusive: Trase raises $107M for health care and defense AI
The company will be in market later this year for a round projected to be in the "hundreds of millions."
Anthropic Veterans’ Startup Seeks to Help Scientists Develop Their Own AI
Mirendil raises $200 million from Andreessen Horowitz and Kleiner Perkins to make AI that can do the job of an AI engineer.
Assort Health Raises $120 Million Series C to Scale Largest Deployment of AI Agents for the Patient Journey
/PRNewswire/ -- Assort Health, the most widely-used AI agents platform for the patient journey, today announced a $120 million Series C led by Menlo Ventures...
Marvin Mims gets brutally honest over Denver Broncos offseason moves
When the Denver Broncos completed their NFL blockbuster trade for Miami Dolphins wide receiver Jaylen Waddle, they moved one step closer to Super Bowl contention. A player of Waddle’s caliber almost certainly raises the ceiling of head coach Sean Payton’s…
Local business raises more than $1K for residents displaced by Brockport apartment fire
SWEDEN, N.Y. (WROC) – After hearing the details of a devastating apartment complex fire in Brockport which displaced more than thirty people, the owners of a business in Sweden decided to step up and ...
Kansas Democratic gubernatorial candidate's union membership sparks political finger-pointing
Democratic candidate Cindy Holscher's membership in the KNEA union raises an alarm in union-endorsed rival Ethan Corson's campaign for governor.
Warton grad who used to pressure wash homes raises $40M to help plumbers, electricians run businesses with AI
George Eliadis, 24, raised venture capital funds from Andreessen Horowitz and Sequoia Capital for Probook, his AI platform for home service businesses.
Wharton grad who used to pressure wash homes raises $40M to help plumbers, electricians run businesses with AI
George Eliadis, 24, raised venture capital funds from Andreessen Horowitz and Sequoia Capital for Probook, his AI platform for home service businesses.
OpenEvidence will add FDA-cleared AI to detect heart disease
In this edition of STAT Health Tech: OpenEvidence adds AI to detect heart disease, and Cadence raises $100 million, and more.
Cadence raises $100 million to automate chronic disease care with regulated AI
Digital health startup Cadence has raised $100 million at a $1.23 billion valuation to expand its chronic disease management program.
Exclusive: Ladder Health raises $7M for developmental care
Ladder is aiming to combat the long waitlists often associated with pediatric services.
Virginia legislators advance $205 billion budget including new tax on data centers
Virginia legislators approved a two-year, $205 billion budget proposal to fund healthcare and public education, provide 4% teacher raises and a 3.5% pay bump to state employees, establish a retail weed marketplace and hedge against decreased federal dollars.
Kojima Says OD Will Push Horror’s Limits, as Todd Howard Gives TES VI Update and Praises Arkane’s Blade
Kojima says OD will push horror’s limits, while Todd Howard gives a The Elder Scrolls VI update and says Arkane is doing great on Blade.
SMI Provider Raises $17M for Expansion Efforts
Vanna Health, a serious mental illness provider, has secured $17 million in a Series B funding round. The San Francisco-based company will use the
Savannah Guthrie praises husband Mike Feldman in rare Father's Day post
"Today" show host Savannah Guthrie shone the Father's Day love light on her husband Mike Feldman, calling her supportive spouse of 12 years the family's "hero."
Scheffler praises Clark's resolve in gutsy US Open triumph
World number one Scottie Scheffler praised playing partner Wyndham Clark for defying New York hecklers as well as formidable Shinnecock to win his second US Open title on Sunday.Scheffler settled for a share of fourth after firing a one-over par 71 to finish on 280 while Clark edged fellow American Sam Burns by one stroke for the title.
Fish consumption advisory raises concerns over ‘Sound Science’ law |…
The Mobile Baykeeper said new fish advisories are one reason the state’s new Sound Science law causes concerns. | Alabama News
Opinion: Is the role of the Alaska Board of Fisheries sustainability or politics?
The recent decision by the Alaska attorney general’s office to overturn several Area M management proposals raises serious concerns about the state’s commitment to sustainable fisheries management.
AI regulation is a mess, and Anthropic is caught in the crosshairs
The latest spat between Anthropic and the government raises a broad concern among AI and safety researchers: There is no consistent framework for regulating AI.
3rd annual Louisville celebrity basketball game raises funds for mental health, suicide prevention
Peyton Siva, Nolan Smith, Ray Spalding, Pedro Bradshaw, Scott Davenport, Tony Williams and Grace Berger were among those playing, coaching and supporting 24 Reasons.
Guinea-Bissau: Opposition leader house arrest raises stakes
Opposition leader Domingos Simoes Pereira remains under house arrest months after the Guinea-Bissau coup, deepening a political crisis and raising tensions with international partners.
Long list of U.S. concessions to Iran raises specter of a 'lost war'
Details of the framework peace agreement were finally shared with the public, revealing a raft of compromises with Tehran long opposed by Republicans.
Architect Labs raises $24 million to take on Broadcom, Marvell custom chip business
Architect Labs said on Thursday it had raised $24 million in seed funding to build a company that will use artificial intelligence to speed and ease the design of custom chips.
Google Releases Free Android Upgrade To Millions: Samsung Galaxy Next
Samsung's Android 17 upgrade is coming to Galaxy phones via One UI 9. But the biggest feature, Gemini Intelligence, raises serious security questions. Here's what to know
Penn State Health raises $51,742 during second annual ‘Let’s Get Ahead’ campaign
Penn State Health raised $51,742 through its second annual “Let’s Get Ahead” campaign during Head and Neck Cancer Awareness Month in April.
Exclusive: Clair Health raises $11.6M for women's health wearable
Wearables giants Oura and Whoop are pushing more deeply into women's health.
Fashion tycoon Bernard Arnault accused of stranglehold over French business press
Arnault’s addition of leading weekly to stable of publications raises concerns about media ownership in France
Australian Predictive Healthcare Startup Raises $46 Million
Sydney-based Airtree Ventures led the financing, joined by Left Lane Capital in New York.
Trump's Iran agreement raises a basic question: Is it actually a deal?
Trump hails Iran memorandum as normalizing relations, but officials say core issues like sanctions relief and nuclear concessions remain for future talks.
Human Cell Atlas leader’s tie to 10x Genomics raises conflict-of-interest questions
As the Human Cell Atlas project marks its 10th anniversary, a leader's ties to a major single-cell RNA sequencing company raise conflict-of-interest questions.
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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