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NVIDIA Unveils "Preset C "DLSS Frame Generation with up to 35% Faster Generation
NVIDIA has updated its DLSS Frame Generation algorithm to be faster and more efficient. In the latest NVIDIA App beta update, rolling out today, the company introduced "Preset C," the fastest Performance Mode for DLSS Frame Generation. NVIDIA demonstrates that this mode can make frame generation...
KINGPIN Says a Connector Dispute With NVIDIA Derailed EVGA's Last Flagship Card
Vince "KINGPIN" Lucido has blamed NVIDIA for the troubled launch of the EVGA GeForce RTX 3090 Ti KINGPIN, the last graphics card to carry his name. In the first video on his new Overclocking Kingpin YouTube channel, the overclocker said he wanted the card to have two 12VHPWR power connectors,...
GTA 6 Leaker Claims to Have Full Build, Threatens to Release It Unless Take-Two Apologizes
The notorious leaker known as Cyberleek is now threatening to release what is claimed to be a playable build of GTA 6 ahead of the game's November 19 launch. According to a post on the leaker's own website, the build supposedly includes the full story mode, playable through to the end credits....
PS2 Discs Now Load on Jailbroken PS5 Consoles Through PS5SX2 Emulator
Developer Sword has added physical disc support to PS5SX2, a native port of the PCSX2 PlayStation 2 emulator for jailbroken PlayStation 5 consoles. The feature arrived as a beta in version 2.01 on October 10, a day after Sword showed it off on X with a clip of a PS2 disc going into a PS5....
NVIDIA Reportedly Ending the RTX 5090, Reserves GB202 Silicon for Workstation GPUs
NVIDIA has reportedly stopped allocating GB202 silicon to the GeForce RTX 5090, according to leaker MEGAsizeGPU (@Zed__Wang) on X. "No more GB202 for 5090, confirmed," the leaker posted, adding in a follow-up that "all future GB202 supplies are RTX Pro exclusive." GB202 is the largest "Blackwell"...
Gears of War: E-Day Sold 168,000 Copies on Steam but Xbox Game Pass Players Generated 130% More Revenue
We recently reported that Gears of War: E-Day wasn't having the best launch week over on Steam, but according to Alinea Analytics's Rhys Elliott, Steam doesn't even account for half of the game's revenue or owner base. The analytics firm estimates that Gears of War: E-Day sold around 230,00...
Arc Raiders Jumps to Six-Month High Player Count With 2.0 Update and Free Weekend
Embark Studios has put in a decent amount of work maintaining and developing Arc Raiders in recent months, with the company recently announcing an upcoming co-op mode slated to launch into testing on October 13 while it continues to iterate on its anti-cheat processes and detection methods. In...
PC Shipments Drop 20.1% in Q3 2026, HP and Dell Hit Hardest
Worldwide PC shipments fell a steep 20.1% year over year in Q3 2026 to 62.7 million units, according to preliminary data from IDC, down from 78.5 million in the same quarter last year. It is the second straight quarterly decline, and a much deeper one than Q2, which IDC now lists as a 3.8% drop....
IT firm’s relocation paves way for latest I-88 warehouse project
The plan spotlights two forces reshaping the suburban office market: Companies upgrading their workspace to adapt to post-pandemic usage and real estate firms redeveloping office properties into warehouses.
Mr GameShow turns Venice game nights into Suncoast business
Founder Andy Geremia joined Suncoast View to talk about the company's game show events
Gears of War: E-Day Launches to Modest Reviews and 31,500 Peak Steam Players
Gears of War: E-Day, the origin story of the long-running Gears of War franchise, launched on Steam, Xbox, and Game Pass, and, although Microsoft has been building hype for the new Gears game for several months leading up to launch day, the game's launch performance on Steam is less than stellar....
OpenAI says teens use ChatGPT for under 15 minutes a day as worries over risks grow
Teens spend under 15 minutes a day on average on ChatGPT, while less than 2% of them interact with the chatbot for over three straight hours, OpenAI said, as technology companies face scrutiny over the risks AI chatbots pose to children.
Food Entrepreneurs Get A Free Crash Course In Growing A Business
At the inaugural CT Food Business Lab, hosted at SCSU and organized by CitySeed, the Hispanic Federation, the Urban League, and CT Food Launchpad.
Leaked GameStop Memo Calls $1,399.99 Used PS5 Pro Pricing "Intentional"
GameStop is now reportedly asking $1,399.99 for a pre-owned PlayStation 5 Pro, which is $500 more than Sony's $899.99 list price for a new one. Consoles with the disc drive attached go for $1,499.99, and GameStop Pro members apparently get the base unit for $1,329.99. An internal memo shared on...
Leak Tips NVIDIA RTX Spark-Powered Microsoft Surface Laptop Specs
Following what appears to have been a series of unfortunate events that led to a roadside laptop find resulting in confirmation that Microsoft will be launching a 20-core NVIDIA RTX Spark Surface Laptop, we now appear to have confirmation that Microsoft will also be launching a Surface Laptop...
Razer Unveils Wolverine V4 Line of Wireless Xbox Controllers
Razer, the leading global lifestyle brand for gamers, today announced the new Razer Wolverine V4 line, including the wireless Razer Wolverine V4 Pro and wired Razer Wolverine V4 Tournament Edition, the next generation of esports controllers officially designed for XBOX and PC. Packed with new...
ASUS Announces New 64GB Configuration of the Ascent GX10
ASUS today announced a new 64 GB configuration of ASUS Ascent GX10, expanding the lineup alongside the existing 128 GB model. This compact AI supercomputer is designed to bring local agentic AI development within reach of more developers, researchers and data scientists. Based on the NVIDIA DGX...
Ace Combat 8: Wings Of Theve Smashes Series Steam Record With Over 52,000 Concurrent Players
Ace Combat 8: Wings of Theve is off to the series' best PC launch by a wide margin. The game came out on October 2 and peaked at over 52,000 concurrent Steam players a day later, according to SteamDB. That is nearly four times the 13,758 that Ace Combat 7: Skies Unknown managed in 2019, while...
How Americans’ Financial Health Is Faring In The “K-Shaped” Economy
Hey all, Jason here. Money20/20 is still two weeks away, but I’ve already started packing (not procrastinating for once!). My calendar is already filling up with various sessions I want to catch, meetings, and of course happy hours, dinners, and other side events. If you’ll be in Vegas and want to catch up, let me know by replying to this email, and we can try to find a time amidst the chaos of the Venetian. A big if not totally unexpected piece of news dropped on Friday: the Independent Community Bankers of America, a trade group that represents smaller U.S. banks, filed a lawsuit against the OCC and Comptroller Jonathan Gould, arguing that the regulator’s move to grant trust bank charters to firms seeking to use them to conduct substantial non-fiduciary activities exceeds the authorities granted to the OCC by Congress. I haven’t had time to fully digest the legal filing or speak to folks in my network about it, but you can expect to see coverage and analysis on it in next week’s newsletter. Subscribe or Support by Upgrading The NerdCon agenda just dropped. It’s stacked. Partner content: Nubank built an AI-first bank. Chime built its own banking core. Figure and Valon are rebuilding the mortgage stack. At NerdCon, you’ll hear from the people behind those bets: what they chose, what they learned, and what they’re still figuring out. The agenda is live, with leaders from Nubank, Chime, OpenAI, Remitly, Mercury, Figure, Valon and more. Follow the mainstage conversations, bring the problem your team is wrestling with to a hands-on workshop, or pull up a chair at a roundtable. Pick your quests. Meet us in San Diego, November 18–20. Fintech Business Weekly readers save 20% with code FBW20. Explore the Agenda Things To Know & Other Good Reads Federal Reserve Board finalizes changes to enhance the transparency and public accountability of its stress test and reduce volatility in its stress test-related capital requirements (Federal Reserve Board of Governors) FDIC Announces Conclusion of Independent Monitorship (FDIC) Modernizing Financial Regulation: Initial Observations from eSLR (Fed Vice Chair for Supervision Michelle Bowman) The Data Version of Godzilla versus Kong: FRED Takes on AI (Fed Governor Christopher Waller) Financing the AI buildout (Brookings) Q3’26: Rules for Banks but Not for Crypto (Fintech Takes Banking) The Inevitability of Local Stablecoins (Lombard Notes) Delusions of AI Governance: The Human-in-the-Loop Comfort Blanket (Fintech Snark Tank) Stripe agrees to acquire Parafin to expand revenue opportunities for platforms and help small businesses grow (Stripe) Listen: Fighting Fraud in the Age of AI, with SEON’s Tamas Kadar (Fintech Business Weekly) How Americans’ Financial Health Is Faring In The “K-Shaped” Economy If there is one overarching theme across the economy and politics in the U.S. at the moment, it’s “affordability.” The term is vague enough to encompass a panoply of factors shaping Americans’ day-to-day lives: rising costs for the hallmarks of being “middle class,” including healthcare, housing, childcare, and education, inflation and rising interest rates, and a job market with the specter of AI hovering over it. At the same time, policy shifts under the Trump administration have resulted in reduced subsidies to those who get health insurance under the Affordable Care Act and new restrictions on qualifying for Medicaid and SNAP, the impacts of which have yet to be fully felt. These factors are contributing to declining consumer confidence and general dissatisfaction with the economy, despite continuing GDP growth and stock market records. This divergence is encapsulated in the idea of the “K-shaped” economy, in which a small proportion of Americans have seen their wealth balloon, while the majority of American households struggle to preserve the lifestyle they have. Perhaps the greatest determinant of which branch of the “K” a household is on is whether their wealth and income are primarily derived from employment vs. from assets. Nearly two decades of low interest rates and, more recently, elevated rates of inflation have benefited asset owners, while those whose income is primarily or solely derived from labor have largely seen real purchasing power stagnate or decline. This is reflected in recent Bureau of Labor Statistics data showing that labor share of U.S. GDP — the fraction of economic output that accrues to workers as compensation in exchange for their labor — dropped to just 52.8% in Q2 2026, the lowest since the BLS began keeping records. In 1947, approximately 2/3rds of economic output accrued to workers; even as recently as 2001, labor’s share of GDP was 64.1%. Against this backdrop, we’ve seen the rise of more credit and credit-like products: cash advance apps, “no-fee” overdraft, earned wage access, and buy now pay later, which are often used as small-dollar short-term borrowing mechanisms to meet immediate consumption needs or pay other bills (eg utilities, cell phone, other debt payments). With the markers of a middle class existence and, increasingly, basic financial stability seemingly out of reach for many, it should be no surprise there’s been an increase in “financial nihilism,” something industry peers like Alex Johnson and Frank Rotman have discussed and analyzed the roots of. The explosion of gambling and gambling-adjacent products and services — often marketed under the guise of being an “investment” — is inextricably intertwined with the rise of financial nihilism. Crypto, sports betting, and, more recently, prediction markets offer an escape or even hope of sorts, like a contemporary, digital version of a scratch-off lottery ticket, while leaving the overwhelming number of people who use such products worse off. Share of Households That Are Financially “Vulnerable” Ticks Up The Financial Health Network’s 2026 Financial Health Pulse® report adds context on how American households are faring. (I linked to this report in last week’s newsletter, but wanted to take time to further unpack the data in the report this week.) The Financial Health Network publishes the report annually, providing insight into how Americans’ financial circumstances are changing over time. The 2026 report is derived from a survey fielded in April and May 2026. The report leverages survey responses to assess indicators of financial health across spending, saving, borrowing, and planning/protecting and to determine a zero to 100 “FinHealth” score. Those with scores between 0 and 39 are considered “Financially Vulnerable,” consumers with scores ranging between 40 and 79 are defined as “Financially Coping,” and those with scores of 80 to 100 are “Financially Healthy.” The report found that moderate improvements in 2025 were reversed, with the share of respondents considered financially “vulnerable” rebounding to 17%. The longitudinal data reflect the impact of pandemic-era programs, like expanded unemployment, cash stimulus payments, and pauses of federal student loan payments. The positive impacts of those programs, as reflected in the Financial Health Pulse reports, had largely disappeared by 2023. While pandemic-era inflation — to be fair, in part caused by the various support and stimulus measures — had come down from as high as 9% in 2022, it has rebounded since the start of Trump’s second term, with tariffs and energy market disruptions owing to the war in Iran pushing prices back up. Specific indicators in the survey that deteriorated from 2025 to 2026 include the share of respondents spending less than their income over the past 12 months, the share paying all bills on time over the past 12 months, the share that have a manageable amount or no debt, the share that are “moderately” or “very” confident their insurance is adequate to cover them in an emergency, and the share that “somewhat” or “strongly” agree that their household plans ahead financially. Unsurprisingly, lower- and moderate-income households are more likely to struggle to pay their bills on time and have any funds leftover to save. The share of low-income households whose income exceeded their spending dropped from 35% in 2025 to 31% in 2026, while the share of upper-income households whose income exceeded expenses remained unchanged at 63%. Households with student loans or revolving credit card debt reported having “a bit more” or “far more” debt than was manageable at rates far higher than those not carrying these types of debts. The share of those with student loan debt indicating their debt load was too high to manage increased from 50% in 2025 to 55% in 2026, while the share of those with revolving credit card debt saying the same ticked up from 51% in 2025 to 54% in 2026. Households that had student loans were markedly more likely to be financially “coping” or “vulnerable” vs. those without student loans. In 2026, 27% of households with student loans were considered financially vulnerable, a jump of 6% points vs. 2025. Households without student loans saw just a 1% point increase (not statistically significant) in those considered financially vulnerable. Households’ perception of the affordability of categories of goods and services paints a stark picture, with less than one-fourth considering higher education affordable, about a third deeming childcare affordable, and less than half viewing healthcare as affordable. Fintech Business Weekly is made possible by the generous support of paying subscribers — bringing you independent analysis of banking, fintech, and crypto without fear or favor. You can support my work by becoming a paying subscriber if you aren’t already. Paying subscribers enjoy: access to the entire archive of nearly six years of newsletters extended versions of the weekly newsletter, with additional content and analysis and (for founding member tier) quarterly personal 1:1 fintech Q&A / strategy calls with me, tapping into my unparalleled knowledge of the intersection of banking and fintech and experience working in the sector, including helping to launch Goldman Sachs’ retail bank Marcus Support Fintech Business Weekly You can also support Fintech Business Weekly by sponsoring a newsletter or podcast, putting you in front of 93,000+ of the most influential decision makers in banking, fintech, and crypto. Learn more about sponsor opportunities or request a media kit by dropping me an email. Democratic Senate Report Highlights How Iran Uses Tether to Evade U.S. Sanctions Iran uses stablecoins, specifically Tether, to evade sanctions, fund regional proxies, and to purchase military drones, a report released last week by the Senate Permanent Subcommittee on Investigations says. The report was authored by committee ranking member Senator Richard Blumenthal (D-CT) and the minority staff. Crypto and stablecoin proponents will often push back on criticism that criminals make use of these assets by arguing that, on an absolute dollar basis, far more illicit funds flow through traditional banking systems and payment rails than via crypto and stablecoins. And while that is likely true, it elides the reality presented in news story after news story: whether state actors — Russia, Iran, North Korea — or criminal groups, those looking to engage in illicit transactions increasingly favor stablecoins and, specifically, Tether (USDT). The report from the Senate Permanent Subcommittee on Investigations released last week adds context to how Iran uses Tether has a lynchpin in its shadow banking system. The report analyzed 846 wallets that have been sanctioned or targeted for seizure, finding that 84% of them transacted exclusively or primarily in Tether. The ability to create near limitless, anonymous wallets and to move funds effectively instantaneously and irreversibly have made crypto a favored financial mechanism for bad actors. Stablecoins solved key drawbacks of bitcoin, namely, the original cryptocurrency’s highly volatile value in dollars. And while Tether (the company) has the technical ability to “freeze” or destroy funds, the company is often limited and reactive in its approach to doing so, the Senate report argues. Tether, which is nominally based in crypto-friendly El Salvador, “has stated that its compliance with OFAC sanctions is ‘voluntary’ and that it follows ‘OFAC guidelines,’” the Senate report says. Owing to these favorable attributes, Tether “became a primary cryptocurrency for Iran, Hamas, Hizballah, and the Houthis beginning in 2023 and has expanded in scale since,” according to the report. Tether’s role in Iran’s shadow banking system, the report says, is enhanced by crypto exchanges like Bybit, Kyrrex, OKX, Gate, and Binance, and through “over the counter” exchanges and hawala networks. The consequences of these financial flows aren’t hypothetical. The Senate report links Tether as a funds transfer mechanism to Iranian proxies in the region, including Hizballah, the Houthis, and Hamas. Tether has also been used to make payments to secure components necessary to manufacture drones, the report says. The report concludes by arguing that “[s]tablecoin issuers with a significant nexus to the United States, particularly those that offer dollar-denominated stablecoins, should be subject to American sanctions law rather than being allowed to hide behind foreign jurisdictions.” Stablecoin issuers like Tether must be held accountable for repeated failures to prevent illicit finance and sanctions violations by law enforcement, the Department of Justice, the Securities and Exchange Commission, and OFAC, the report argues. [Paying Subscriber Exclusive] OUSD Goes Live, Make Your Own Neobank, U.S. Sanctions Russia’s A7 Network As “Transnational Criminal Organization” OpenUSD, the stablecoin issued by the Open Standard consortium that includes Stripe, Visa, Mastercard, core providers, crypto firms, and numerous banks, went live last week. Social commerce platform Whop raised eyebrows in fintech by offering creators on its platform the ability to launch their own neobanks, which the company describes as “great businesses that are easy to run,” in just 15 minutes. And OFAC and FinCEN target Russia’s “shadow banking” A7 Network — more on these stories after the paywall.
Warriors’ Former All-Star Suddenly Emerges as Potential Trade Candidate
The Golden State Warriors could be parting ways with a former All-Star they acquired last season. According to NBA insider Brett Siegel of ClutchPoints, the Warriors’ top trade candidate entering the 2026-2027 NBA season is Kristaps Porzingis because his $20 million salary matches, and only $3 million is guaranteed for next season, essentially making it […] The post Warriors’ Former All-Star Suddenly Emerges as Potential Trade Candidate appeared first on HEAVY.
Jagex Announces RuneScape 4, a New MMO Built in Unreal Engine
Jagex has announced a fourth RuneScape MMO at RuneFest 2026. It currently goes by the working title RS4, though most people are already calling it RuneScape 4. The game is being built in Unreal Engine, and Jagex hasn't said which version. It's the first numbered follow-up since RuneScape 3...
Final Fantasy 7 Revelation Director Says He "Did His Best" to Fight for a Physical Release
Final Fantasy 7 Revelation is getting a physical edition, and it seems director Naoki Hamaguchi had to argue for it. He told Radio Times that he pushed Square Enix for a boxed release, while admitting the product lineup is the publishing team's call. On PS5 and Xbox Series X, the disc reportedly...
NVIDIA Raises Shield TV Pro Price to $299, Discontinues Standard Shield TV
NVIDIA has raised the price of the Shield TV Pro from $199.99 to $299.99, effective October 2. The streaming box launched in October 2019 at $199.99 and held that price for almost seven years. Earlier this year, NVIDIA promised to keep updating the Shield TV, with hardware engineering SVP Andrew...
Used Ryzen 7 5800X3D Gets Buyer Locked Out of Valorant Due to Previous Owner's Cheating
Buying a used Ryzen 7 5800X3D CPU has apparently locked its new owner out of Valorant. Reddit user After-Cartoonist-196 posted on r/PCBaumeister that they bought the chip through the German classifieds site Kleinanzeigen and have owned it since September 21. The CPU apparently works fine....
Sunland Park residents raise health concerns over proposed concrete plant near homes
Residents living near the intersection of Pete Domenici Hwy and McNutt Rd in Sunland Park are concerned about a proposed concrete batch plant near neighborhood.
ASUS ROG Edition 20 - Celebrating 20 years of Republic of Gamers
ASUS is celebrating 20 years, with its "Edition 20" products that are pure enthusiast excess in the best possible way, including a custom AMD Ryzen X870E board & AIO, GeForce RTX 5090, 3000 W PSU, open-frame case and pairing it with a high-end OLED into one beautiful showcase.
NVIDIA Launches DGX Spark 64 GB Desktop AI Systems
Local AI is becoming more useful by the token. As AI agents move from experiments into everyday development, increasingly capable open models are shrinking to fit on more devices, giving builders more to run locally. Coming this month, NVIDIA DGX Spark will be available with 64 GB of unified...
Gears of War: E-Day Performance Benchmark Review
Gears of War: E-Day is a prequel set 14 years before the original game. Built on Unreal Engine 5 with RTX Mega Geometry, DLSS 4.5, FSR 4, XeSS, and ray tracing, we examine graphics quality, VRAM usage, upscaling options, and how it performs across a wide range of modern GPUs.
Resident Evil 5 and 6 Remakes Seemingly Confirmed by Capcom Exec
It seems as though the future of Resident Evil remakes is in flux, with it initially being reported that Resident Evil 5 and 6 would not be getting remakes following the expected Code Veronica and Resident Evil 1 remakes. However, comments by Jun Takeuchi, a franchise veteran who has served as...
Joelinton Returns To Training After Recovering From Foot Injury
The Brazilian powerhouse brings his physical presence back to Tyneside, handing Matthias Jaissle a vital tactical boost as the midfield linchpin nears a return to competitive action.
Xbox Disc-To-Digital Officially Exits Testing
The Xbox Disc-to-Digital licensing program recently launched to insiders, effectively paving the way to a discless future for Xbox, while still allowing the brand to market its console as backwards compatible. Following just over a month of public testing, Microsoft has just announced that the...
Amid PlayStation 5 Pro Shortages, Sony Implements Lottery System Based on Playtime
No one is exempt from the global DRAM shortage, and today Sony confirmed there might be a way for enthusiastic gamers to purchase the PlayStation 5 Pro console at MSRP. In Japan, Sony is running a lottery system that explicitly allows gamers with 60 hours of playtime to purchase the console....
Winners Named in St. Louis County Library Small Business Launchpad
Ayers among judges, Mulvihill facilitated during program St. Louis County Library recently held its Small Business Launchpad, an 8-week entrepreneurship program designed for formerly incarcerated individuals who are interested in…
Dennis Haskins, 'Saved by the Bell' principal, dies at 75
The actor became a fixture of the beloved 1990s teen sitcom as Principal Richard Belding, known for his "Hey, hey, hey" catchphrase.
Palm Beach residents appointed to Cox Science Center board of trustees
Palm Beach residents Deborah Norville, Bill Roberts and Thomas Rosin are among seven new board members of the Cox Science Center & Aquarium.
Framework Desktop with Ryzen AI Max+ Pro 495 Gets Official Pre-Order Date
After teasing the AMD Ryzen AI Max+ Pro 495 upgrade to the Framework Destkop mini PC, Framework has officially announced that pre-orders for the SFF desktop will start on Wednesday, 30 September. The announcement came in a post on the OEM's official X account, where it also confirmed that, as is...
Analysis | The 9 Senate seats most likely to flip party control in November
Democrats need to flip several in red states to win back the Senate majority. Here are their best chances.
Zhongguancun Science-Tech Leasing Co To Purchase CHP Equipment For RMB71.21 Mln
Zhongguancun Science-Tech Leasing Co Ltd HKEX:1601:
Experimental Emulator Brings Nintendo Switch Games to Jailbroken PS5 Consoles
An unofficial port of the Eden Nintendo Switch emulator is now running natively on jailbroken PlayStation 5 consoles. Developer BlackBearReloaded released ProsperoEden, which adapts Eden, itself a fork of the now-defunct Yuzu project, to run directly on Sony's hardware as homebrew rather than...
Modder Squeezes 74% More Performance Out of DLSS 5 on AMD Radeon in One Day
Modders working on bringing NVIDIA's DLSS 5 Neural Rendering to AMD Radeon GPUs just had their busiest day yet. The developer behind the DLSS-NR-on-AMD tool shipped two new versions within 24 hours, Alpha 0.3.3 and Alpha 0.4.0, together adding roughly 74% performance on Radeon hardware, according...
Glen Powell, Michelle Randolph enjoy Texas-Tennessee matchup
Glen Powell and Michelle Randolph are bringing their love to the football field. Powell and Randolph were beaming at one another while they were in attendance at the University of Texas and University...
Court Orders Reddit Moderator to Pay Nintendo $4.5 Million Over Switch Piracy
A federal court in Washington has ordered Reddit moderator James "Archbox" Williams to pay Nintendo $4.5 million in damages over alleged Nintendo Switch piracy. US District Judge Lauren King granted Nintendo's motion for default judgment in full on September 23, along with a permanent injunction...
Microsoft CEO Says Xbox's "Streamlining" Is "Great To See" Following Recent Layoffs
Microsoft CEO Satya Nadella called Xbox's ongoing job cuts "great to see," commenting on the restructuring led by Xbox CEO Asha Sharma. The remark follows Xbox's latest layoffs, which cut 268 more jobs on top of the 1,600 eliminated earlier this year, part of a plan that has already folded...
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Former player Drew Brees nearly came out of retirement last season to make a stunning return for the Denver Broncos in the AFC Championship Game after starting quarterback Bo Nix suffered a serious ankle injury in the divisional round. With the team facing a significant void ahead of a crucial matchup against the New England Patriots, former New […] The post Broncos: Brees reveals just how fast he knew he was too cooked to return for AFC Championship Game appeared first on ClutchPoints.
Broncos news: Denver makes move after pathetic performance vs. Chiefs
The Denver Broncos didn’t wait long to make a roster move after getting embarrassed on national television. According to DNVR’s Zac Stevens, Denver is re-signing wide receiver Lil’Jordan Humphrey to its 53-man roster following a procedural move that resulted in his release on Monday. Humphrey was not expected to play against Kansas City, but his […] The post Broncos news: Denver makes move after pathetic performance vs. Chiefs appeared first on ClutchPoints.
Governor announces $104 million in rural health grants
Governor Tate Reeves announced 167 awards totaling $104,115,146 through the Mississippi Rural Health Transformation Program. The awards are part of Mississippi’s $205.9 million first-year implementation budget, which will be allocated this year.
Fantasy Football D/ST Rankings: Week 2 2026
Even after losing its starting quarterback, the Seattle Seahawks defense stood up and performed in Week 1. And the Cincinnati Bengals delivered a surprise . But it’s on to Week 2, and here are the fantasy football defense and special teams rankings for the 2026 season. It looks like there are offenses to fear in Week 2. Most notably, the Bears. So […] The post Fantasy Football D/ST Rankings: Week 2 2026 appeared first on ClutchPoints.
Fantasy Football Running Back Rankings: Week 2
Week 1 offered fantasy football managers plenty of clues about which running backs are positioned for monster seasons. Those early usage patterns are already shaping the Week 2 rankings. Jahmyr Gibbs leads the charge after combining explosive rushing production with a significant receiving role. Derrick Henry once again looks like the centerpiece […] The post Fantasy Football Running Back Rankings: Week 2 appeared first on ClutchPoints.
UFC news: Nate Diaz still open to Conor McGregor trilogy
Almost a decade after their last two UFC fights, Nate Diaz is still open to facing Conor McGregor . McGregor and Diaz faced off against each other in 2016 at UFC 196 and UFC 202. With both men having secured one victory each, a rubber match is required to decide the ultimate winner. Nate Diaz has experienced some well-deserved paydays outside the […] The post UFC news: Nate Diaz still open to Conor McGregor trilogy appeared first on ClutchPoints.
Chiefs' Kenneth Walker III already looks like the biggest free agent win of 2026
On a night where everything that could go right for the Kansas City Chiefs did go right, it was running back Kenneth Walker III who emerged as the biggest star of the team following their 31-10 victory over the Denver Broncos in their season-opener. Walker drew plenty of attention after he carried the ball for 60 yards en route to a touchdown that […] The post Chiefs' Kenneth Walker III already looks like the biggest free agent win of 2026 appeared first on ClutchPoints.
Yankees news: Austin Wells offers bold All-Star rotation take
The New York Yankees secured their place in the 2026 postseason after the Toronto Blue Jays lost 8-3 to the Detroit Tigers. Following an 8-3 road win against the Minnesota Twins on Monday night, catcher Austin Wells complimented the club’s starting rotation who has been a major key to their success. “They’re the best in baseball,” Wells remarked. […] The post Yankees news: Austin Wells offers bold All-Star rotation take appeared first on ClutchPoints.
Chiefs news: Kenneth Walker leads Kansas City feat not seen since 2023
When the Kansas City Chiefs acquired running back Kenneth Walker III in free agency in March, many felt that the team suddenly had a cheat code. Well, that was exactly what Walker looked like for the Chiefs in their victory over the Denver Broncos, 31-10, at Arrowhead Stadium on Monday. The 25-year-old star was terrific in his much-anticipated […] The post Chiefs news: Kenneth Walker leads Kansas City feat not seen since 2023 appeared first on ClutchPoints.
Padres news: Jackson Merrill opens up about what sparked turnaround
Center fielder Jackson Merrill entered September 14’s game in Colorado with 12 hits in his previous six games, including three home runs amid the San Diego Padres’ pursuit of a National League Wild Card spot . Merrill shouldered plenty of blame for the Padres’ struggles earlier this summer but is now back on track in large part due to his changed […] The post Padres news: Jackson Merrill opens up about what sparked turnaround appeared first on ClutchPoints.
Broncos news: Drew Brees nearly unretired to play playoff game for Denver
Hall of Famer Drew Brees came remarkably close to returning to the NFL last season after the Denver Broncos lost quarterback Bo Nix to a fractured ankle in their divisional-round overtime win over the Buffalo Bills, ESPN’s Adam Schefter reported Monday. With the AFC Championship Game against the New England Patriots approaching, then-Broncos […] The post Broncos news: Drew Brees nearly unretired to play playoff game for Denver appeared first on ClutchPoints.
Packers news: Could Tucker Kraft be NFL's best tight end?
There were not many good things that the Green Bay Packers could take away from their Week 1 loss against the Minnesota Vikings. Some of the s ame problems they dealt with last season came back to haunt them, one of them being falling apart in the fourth quarter. The Vikings were able to run away with the game, scoring 22 points in the fourth, […] The post Packers news: Could Tucker Kraft be NFL's best tight end? appeared first on ClutchPoints.
OpenRGB 1.0 Launches for Open-Source RGB Customization on Windows, Linux, and macOS
RGB control software has long been a pain point of gamers, with background apps and clunky UIs frequently coming up in discussions about gaming mice, keyboards, speakers, monitors, among many more. OpenRGB is a project that hopes to cut through some of that noise and provide a cross-platform...
Chiefs news: How Patrick Mahomes predicted his Week 1 return
The Kansas City Chiefs enter Week 1 against the Denver Broncos with Patrick Mahomes back under center after months of recovery from a knee injury . Mahomes’ injury could have changed Kansas City’s season before it started, but the quarterback had one answer from the beginning. According to The Athletic’s Jesse Newell, Mahomes told Andy Reid exactly […] The post Chiefs news: How Patrick Mahomes predicted his Week 1 return appeared first on ClutchPoints.
NVIDIA Unveils RTX PRO 5500 "Blackwell" Workstation GPU with 84 GB GDDR7 Memory
NVIDIA today quietly added another card to its pro-viz product lineup with the RTX PRO 5500 "Blackwell" workstation GPU edition. Featuring 84 GB of GDDR7 memory, it is equipped with a GB202 die that includes 21,760 CUDA cores. This is the same CUDA core count as the consumer GeForce RTX 5090 SKU,...
Cardinals news: Jacoby Brissett's powerful Jeremiyah Love verdict
The Arizona Cardinals pulled off one of the biggest stunners of Week 1, beating the Los Angeles Chargers on the road 26-14 in what looked like the perfect blueprint for coach Mike LaFleur’s team going forward. The offense wasn’t perfect, but it had its fair share of strong performances, including a big game from Trey McBride that pulled him close […] The post Cardinals news: Jacoby Brissett's powerful Jeremiyah Love verdict appeared first on ClutchPoints.
Cowboys news: Dak Prescott drops blunt explanation for ugly INT
The start of the 2026 NFL season did not go according to plan for the Dallas Cowboys. Facing their division rival New York Giants in Week 1 of the new campaign, the Cowboys failed to execute when it mattered the most as they suffered a 28-20 defeat. Quarterback Dak Prescott, in particular, was not at his best — completing just 22 of his 34 passes […] The post Cowboys news: Dak Prescott drops blunt explanation for ugly INT appeared first on ClutchPoints.
Bears news: D'Andre Swift's take on 59-point explosion should strike fear for opponents
D’Andre Swift and the Chicago Bears made incredible history after beating down the Carolina Panthers in a 59-37 win on Sunday afternoon. Swift has been playing in the NFL since 2020, starting his third year with the Bears. He shines as their leading rusher, having found comfort there with his production as a versatile running back. Swift dominated […] The post Bears news: D'Andre Swift's take on 59-point explosion should strike fear for opponents appeared first on ClutchPoints.
Cardinals news: Mike LaFleur drops perfect description of Chargers takedown
Mike LaFleur is proud to begin his head coaching career with a win after leading the Arizona Cardinals to a 26-14 road upset win over the Los Angeles Chargers on Sunday afternoon. LaFleur started the first year of his head coaching career in the NFL. He served in multiple positions in college football and the pros, most recently being the Rams’ […] The post Cardinals news: Mike LaFleur drops perfect description of Chargers takedown appeared first on ClutchPoints.
Todd Monken's Browns must end this Deshaun Watson charade immediately
The Cleveland Browns looked dreadful during their season opener on Sunday. Jacksonville smashed Cleveland 34-10 in a game that was never close. Cleveland’s Deshaun Watson-led offense never looked dangerous throughout the game. Now the Browns will have some tough questions to answer leading up to Week 2. Browns head coach Todd Monken defended Watson […] The post Todd Monken's Browns must end this Deshaun Watson charade immediately appeared first on ClutchPoints.
Vikings news: Kyler Murray injury means it's Carson Wentz time
The Minnesota Vikings have not had a dreamy start to the 2026 season. Vikings QB Kyler Murray threw an interception on his first pass attempt since joining Minnesota this offseason. Now the situation went from bad to worse after Murray suffered what could become a serious injury. Murray is currently being evaluated for a concussion , per ESPN’s […] The post Vikings news: Kyler Murray injury means it's Carson Wentz time appeared first on ClutchPoints.
Guardians news: Jo Adell makes franchise history with rocket HR
The Cleveland Guardians have been praised for picking up outfielder Jo Adell ahead of this year’s Major League Baseball trade deadline. Adell has made an immediate impact in Cleveland, and that continued on Sunday. He blasted a moonshot that made franchise history . “Jo Adell!! 116.8 mph! That’s Cleveland’s hardest-hit home run under Statcast […] The post Guardians news: Jo Adell makes franchise history with rocket HR appeared first on ClutchPoints.
Yankees news: Gerrit Cole seeking answers after getting booed during latest start
With the New York Yankees on the verge of clinching a postseason spot , the time has yet to come after the team lost 12-2 to the New York Mets on Saturday, which included another disappointing outing from pitcher Gerrit Cole. As the Yankees and Cole gear up for the playoffs, the star pitcher would get real about his recent outings and what needs to […] The post Yankees news: Gerrit Cole seeking answers after getting booed during latest start appeared first on ClutchPoints.
Diablo 5 Officially Revealed at BlizzCon 2026, Set to Arrive Spring 2029
Blizzard has officially announced Diablo 5 at BlizzCon 2026, confirming a Spring 2029 release window for the next mainline entry in its action RPG series. The reveal came during the event's opening ceremony alongside a cinematic marking Diablo's 30th anniversary. According to game director Joe...