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CDC tightens home monitoring guidance for high-risk hantavirus contacts
People in the “high-risk” category are instructed to stay home and limit contact with others, avoid being in buildings other than their home and avoid visitors to their residences. They are also supposed to coordinate any essential travel with their state or local health department.
Biggs Institute at UT Health San Antonio to lead $2.5 million national, multi-site study on dementia with Lewy bodies
Teaming with UF, UCSF and VCU to improve detection, bring hope Contacts: UT Health San Antonio, Steven Lee, (210) 450-3823, lees22@uthscsa.edu University of Florida, Jill Pease, (352) 273-5816, jpease@PHHP.UFL.EDU University of California San Francisco, Suzanne Leigh, (415) 476-2993, suzanne.leigh@ucsf.edu Virginia Commonwealth University, Leigh Farmer, (804) 828-7028, forresterlg@vcu.edu SAN ANTONIO, July 21, 2026 – The Glenn […]
iOS 27.2 Could Save Your Marriage
The iOS 27.2 beta that Apple released today adds a feature that reminds you it's your anniversary when you call someone, as long as you've added the date in the Contacts app. On the date of your anniversary, when you go to call the person, you'll see a reminder that it's an important day so you don't forget to say something. The anniversary alert uses Call Context, a feature Apple added in iOS 27.
EAST TEXAS POLITICS: Texas ag commissioner contacts White House over USDA screwworm handling
Sid Miller criticizes federal response to New World screwworm outbreak
Your iPhone Gets Stolen. Then the Hacking Begins
A bustling underground ecosystem is providing criminals with the tools to unlock iPhones—and wage phishing attacks against their contacts to access bank accounts and more.
Burlington signs suggest 911 alternatives for mental health, drug call
The city is set to print 100 or so signs for about $3,000 that will include a wide range of contacts for handling mental health, drug and other calls.
Business Restructuring Review Vol. 25 No. 4 July-August 2026
In This Issue New York Bankruptcy Court: Premature Allegations of Creditor Mistreatment Insufficient to Deny Chapter 15 Recognition of Foreign Restructuring Proceeding In In re ARD Finance, S.A., No. 25-12794 (MG), 2026 WL 817458 (Bankr. S.D.N.Y. Mar. 25, 2026), the U.S. Bankruptcy Court for the Southern District of New York was presented with a petition seeking chapter 15 recognition of Luxembourg's recently enacted bankruptcy law governing judicial reorganization proceedings. The court granted the petition, turning aside challenges to recognition voiced by a creditor group arguing that recognition should be denied based upon allegations of unfairness to creditors in the Luxembourg proceeding that would make recognition manifestly contrary to U.S. public policy. According to the bankruptcy court, recognition was warranted because: (i) the rules and procedures governing the proceeding under Luxembourg law were fundamentally fair; (ii) the petition otherwise satisfied chapter 15's recognition requirements; and (iii) the creditor group's allegations were premature, given the fact that the Luxembourg court presiding over the debtor's restructuring proceeding had not confirmed a restructuring plan, and all creditors had the right to participate fully and voice their objections in the proceeding (including the right to appeal an order approving a plan). [read more …] Florida Bankruptcy Court Examines Scope of Discovery in Chapter 15 Cases In In re Banco Master, S.A., No. 25-24568-SMG, 2026 WL 931729 (Bankr. S.D. Fla. Apr. 6, 2026), the U.S. Bankruptcy Court for the Southern District of Florida granted in part and denied in part post-recognition motions filed by an insider of a foreign debtor seeking to bar or limit discovery sought by the debtor's foreign representative concerning allegedly voidable transfers involving the debtors' U.S. real property. According to the court: (i) although chapter 15 includes its own discovery provisions among the relief that may be granted to a foreign representative, the expansive discovery available in cases under other chapters of the Bankruptcy Code is also available in chapter 15 cases; (ii) the discovery sought by the foreign representative was permissible; (iii) discovery regarding matters that were the subject of a pending adversary proceeding had to be undertaken under the more restrictive rules applicable to such proceedings; and (iv) a discovery request would be barred to the extent that it sought production of documents or testimony from a subpoenaed entity that exceeded the geographic limitations specified in such rules. [read more …] Delaware District Court Affirms Chapter 15 Recognition Order Enforcing Nonconsensual Third-Party Releases In U.S. Int'l Dev. Fin. Corp. v. Credito Real S.A.B. de C.V. SOFOM, E.N.R. (In re Credito Real S.A.B. de C.V. SOFOM, E.N.R.), 677 B.R. 192 (D. Del. 2026), appeal filed, No. 26-2356 (3d Cir. June 5, 2026), the U.S. District Court for the District of Delaware affirmed a bankruptcy court order granting chapter 15 recognition to a Mexican "concurso mercantile" proceeding and enforcing nonconsensual third-party releases approved by the Mexican court. Agreeing with the bankruptcy court that the releases were not manifestly contrary to U.S. public policy, the district court concluded: "It is well settled that U.S. bankruptcy courts can give effect to foreign orders in recognized foreign proceedings pursuant to the authority granted in Chapter 15, even when those orders contain relief unavailable under U.S. law. [The appellant's] arguments misconstrue the Supreme Court's narrow holding in Purdue, applicable in Chapter 11 cases, as well as the statutory framework of Chapter 15 and its core policy objectives. Accordingly, I will affirm the Enforcement Order." The ruling has been appealed to the U.S. Court of Appeals for the Third Circuit. [read more …] Fifth Circuit: Bankruptcy Court, Not State Court, Had Jurisdiction to Allow or Disallow Administrative Expense Claim In Storey Minerals Ltd. v. EP Energy E&P Co., LP (Matter of EP Energy E&P Co., LP), 169 F.4th 609 (5th Cir. 2026), the U.S. Court of Appeals for the Fifth Circuit affirmed lower courts' rulings disallowing a creditor's administrative expense claim. It also rejected the creditor's argument that, because the claims were predicated on state law, a state court should adjudicate the merits of the state law causes of action before the bankruptcy court could allow or disallow the claim as an administrative expense. According to the Fifth Circuit, even though the causes of action were based on state law, the bankruptcy court had jurisdiction to determine whether the creditor's claims should be conferred with administrative expense priority in the debtors' chapter 11 case. [read more …] New York Bankruptcy Court: Dismissal of Involuntary Chapter 11 Case Filed Prior to Commencement of Foreign Restructuring Proceeding Unwarranted In In re Xinyuan Real Estate Co. Ltd., No. 25-10745 (PB), 2026 WL 592250 (Bankr. S.D.N.Y. Mar. 3. 2026), the U.S. Bankruptcy Court for the Southern District of New York considered the bona fides of an involuntary chapter 11 petition filed by certain holders of U.S. dollar-denominated notes against a holding company for a group of Chinese property development companies that filed a restructuring proceeding in the Cayman Islands after the noteholders filed the involuntary chapter 11 petition. The court denied the debtor's motion to dismiss the chapter 11 case. Given the timing of the filing of the Cayman Islands restructuring proceeding, the absence of any progress in the proceeding for seven months, the debtor's need to restructure notes governed by U.S. law, and the debtor's lack of any meaningful contacts to the Cayman Islands, dismissal of the chapter 11 case was unwarranted under the applicable provision of the Bankruptcy Code, international comity, or the doctrine of forum non conveniens. [read more …] Bankruptcy Court Evaluates Trustee's Authority to Sell Avoidance Actions and Right of Target Defendants to Object In In re Law Enf't Officers Sec. Union, No. 24-70277-JAD, 2026 WL 560452 (Bankr. W.D. Pa. Feb. 27, 2026), a chapter 7 trustee sought court approval to sell certain avoidance actions to a creditor of the debtor's estate. Potential targets of the subject avoidance actions objected, arguing that such claims were nontransferable powers of the trustee rather than saleable estate property and urging the court to approve their competing settlement with the trustee. The U.S. Bankruptcy Court for the Western District of Pennsylvania disagreed with the potential defendants, holding that they lacked standing to object to the proposed sale, that avoidance actions are indeed estate property, and that the sale—rather than the settlement—best served the estate's interests. [read more …] U.S. Supreme Court Bankruptcy Roundup in Brief In Keathley v. Buddy Ayers Construction Inc., No. 25-6, 2026 WL 1686028 (U.S. June 11, 2026), the U.S. Supreme Court overturned a Fifth Circuit decision judicially estopping a chapter 13 debtor from asserting a personal injury claim against a construction company because the debtor failed to disclose the claim during his bankruptcy case. In so ruling, the Court held that "[t]he Fifth Circuit erred by artificially narrowing its inquiry to whether the debtor had knowledge of the underlying facts or a potential motive to conceal the claim." It represents the first time that the Court has applied judicial estoppel in the bankruptcy context, although it has suggested in other contexts that it may be inappropriate where an inconsistent legal position resulted from "inadvertence or mistake." Also in June, the Court denied petitions for certiorari in a few notable bankruptcy cases. [read more …] Newsworthy Heather Lennox (Cleveland/New York) (Star Individual), Bruce Bennett (Los Angeles) (Senior Statesperson), Kevyn D. Orr (Washington) (Eminent Practitioner), Gregory M. Gordon (Dallas) (Band 1), Carl E. Black (Cleveland), Corinne Ball (New York) (Senior Statesperson), Brad B. Erens (Chicago), Jeffrey B. Ellman (Atlanta), T. Daniel Reynolds (Cleveland), and Dan T. Moss (Washington/New York) were recognized as leading lawyers in the practice area Bankruptcy/Restructuring in the 2026 edition of Chambers USA: The World's Leading Lawyers for Business. The 2026 edition of Lawdragon 500 Leading Bankruptcy and Restructuring Lawyers ranked the following lawyers: Corinne Ball (New York) (Hall of Fame), Bruce Bennett (Los Angeles), Carl E. Black (Cleveland), Jeffrey B. Ellman (Atlanta), Brad B. Erens (Chicago), Gregory M. Gordon (Dallas), Heather Lennox (Cleveland/New York), Joshua M. Mester (Los Angeles), and Kevyn D. Orr (Washington). Fabienne Beuzit (Paris) and Jasper Berkenbosch (Amsterdam) were among the "Leading Individuals" ranked in the 2026 edition of The Legal 500 EMEA guide in the field of Restructuring and Insolvency or Insolvency. Rodolphe Carrière (Paris) was named a "Next Generation Partner" in the practice area Insolvency. Sid Pepels (Amsterdam) was selected by Global Restructuring Review's 40 under 40 2026. He was identified as a Rising Star within the global cross-border restructuring community. Global Restructuring Review is a leading digital subscription service, news outlet, and information platform dedicated exclusively to cross-border insolvency and corporate restructuring law. Fabienne Beuzit (Paris), Rodolphe Carrière (Paris), and Isabelle Maury (Paris) were recognized in the 2027 edition of The Best Lawyers in France™ in the practice area Insolvency and Reorganization Law. An article written by Corinne Ball (New York) titled "Comity and Fairness are Critical to Granting Additional Assistance under Chapter 15: A Canadian Reverse Vesting Order and Related Releases in Proceedings Involving Canadian and U.S.-Affiliated Companies Are Approved" was published in the June 24, 2026, edition of the New York Law Journal. An article written by Caitlin K. Cahow (Detroit) titled "New York Bankruptcy Court Weighs In on Adequate Assurance of Future Performance under Assigned Leases and Chapter 11 Plan Exculpation Provisions" was published on June 8, 2026, in Lexis Practical Guidance. An article written by Trisha L. Mowbray (Real Estate; Chicago) and Ryan Sims (Washington) titled "Chapter 11 Plan that Abridged Non-Debtor Lessee's Rights to Remain in Possession After Rejection Unconfirmable as Having Been Proposed in Bad Faith" was published on June 16, 2026, in the Harvard Law School Bankruptcy Roundtable. An article written by Dan T. Moss (Washington/New York), Corinne Ball (New York), Isel M. Perez (Miami), and David S. Torborg (Washington) titled "Texas Bankruptcy Court Adopts Barnet Rule Requiring Foreign Debtor to Have U.S. Assets to Be Eligible for Chapter 15 Relief" was published on June 10, 2026, in Lexis Practical Guidance. An article written by Daniel J. Merrett (Atlanta) and Nathaniel Parr (Atlanta) titled "Southern District of Texas Clarifies Post-Purdue Course for Consensual Third-Party Releases and Gatekeeping Provisions" was published on June 11, 2026, in Lexis Practical Guidance. An article written by Corinne Ball (New York) titled "LMEs, Sophisticated Investors and Equitable Mootness: The Fifth and Third Circuits Warn Against Testing the Limits of Chapter 11" was published in the June 2026 issue of the American Bankruptcy Institute Journal. Nicholas J. Morin (New York) was quoted in an article titled "Serta Ruling Offers Damages Road Map in Lender-on-Lender Disputes," published by Bloomberg Law on July 7, 2026. The article discussed U.S. Bankruptcy Judge Christopher Lopez's July 7, 2026, ruling that participating lenders in Serta Simmons Bedding's 2020 non-pro rata uptier exchange breached the credit agreement's ratable-sharing provision, and awarding excluded lenders more than $261 million in damages. The opinion resolves six years of litigation related to Serta's 2020 transaction, where it raised $200 million in new financing and exchanged $1.2 billion of term loans for $875 million in superpriority debt. Judge Lopez found that the debt-for-debt exchange constituted a "payment" under the credit agreement, requiring proportional sharing among lenders, and dismissed various defenses raised by the participating lenders. The case is Serta Simmons Bedding LLC v. AG Centre Street Partnership (In re Serta Simmons Bedding LLC), 2026 WL 1968535 (Bankr. S.D. Tex. Jul. 7, 2026). The New York Law Journal has recognized Andrew M. Butler (New York) as a 2026 "Rising Star" in Restructuring/Bankruptcy as part of the New York Legal Awards. The Rising Star category recognizes New York's most promising lawyers age 40 and under who have distinguished themselves through exceptional legal work, leadership, and contributions to the profession. Lawyer Spotlight: Daniel J. Merrett Dan Merrett, a partner in the Atlanta Office, has spent nearly 20 years representing all manner of stakeholders in complex corporate restructurings and chapter 11 reorganizations. His practice extends to related transactions and disputes involving acquisitions; divestitures; credit facilities; securities; environmental obligations; and vendor, employee, and governance matters. Dan has substantial experience managing mass tort liabilities, including the restructurings and related chapter 11 cases of affiliates of Georgia Pacific and Johnson & Johnson, implemented to resolve asbestos and talc liabilities. He also represents key parties in energy and infrastructure matters, including facility owners, EPC contractors, and joint-venture parties. Dan was a key player in the restructuring teams in the historic bankruptcies of the City of Detroit and Chrysler. His other significant representations in chapter 11 cases include AFA Foods, Alpha Natural Resources, Dana Corporation, M&G Chemicals, McDermott International, Monster/CareerBuilder, Transtar Industries, and Westinghouse. He is licensed in both the United States and England & Wales and recognized in restructuring by Chambers USA and Best Lawyers.
EAST TEXAS POLITICS: Texas ag commissioner contacts White House over USDA screwworm handling
Texas Agriculture Commissioner Sid Miller criticized the USDA’s response to the New World screwworm on this week’s edition of East Texas Politics on East Texas Now with Blake Holland. Smith County Pct. 3 Commissioner J. Scott Herod, a cattle rancher and owner of Cut Beef in Tyler, also appeared on the program. Plus, State Rep. Cody Harris talks data center water usage.
WhatsApp Gets New CarPlay App
Facebook-owned messaging app WhatsApp was today updated with expanded support for CarPlay. CarPlay users are able to more easily call and message their friends and family members in WhatsApp directly from the car interface. WhatsApp had CarPlay integration before, but with limited Siri-based functionality. The new app has a full native CarPlay interface with a list of recent chats and call history, along with a tab for favorite contacts.
iOS 26.6 now available for iPhone with these changes
iOS 26.6 is now available for iPhone with security fixes, a Spotlight upgrade for iOS 27, and a new blocked contacts alert.
Five Measles Cases Identified in Fremont County, Bringing Wyoming’s Total to Fourteen - Wyoming Department of Health
The Wyoming Department of Health (WDH) has identified five cases of measles among Fremont County residents. All five cases are part of the same chain of transmission, with the initial exposures to measles occurring outside the state and potential subsequent spread among close contacts. The five cases include both adults and children. All individuals were […]
Roma in contact with free agent Matteo Darmian
A new name has been linked with Roma.According to TUTTOmercatoWEB.com, in recent weeks there have been contacts between Roma and Matteo Darmian, a defender released after several positive seasons with...
Israel’s Strategy to Break Its Isolation in Latin America
As part of Israel’s “Year of Latin America” strategy announced for 2026, Tel Aviv has increased its contacts with the Uruguayan government.
Authorities scramble to limit hantavirus outbreak, trace contacts around globe
Dutch authorities said a flight attendant is being tested as the race is on to trace passengers who left a cruise ship and two flights linked to an ill woman.
UT Health San Antonio announces $6.5 million gift to strengthen pediatric health workforce through new Harvey E. Najim Pediatric Health Scholars Program - UT Health San Antonio
Contacts: Monica Taylor, UT Health San Antonio, taylorm1@uthscsa.edu, 210-450-8970 Eileen Teves, UT Health San Antonio, tevese@uthscsa.edu, 210-450-7239 SAN ANTONIO, March 26, 2026 – UT Health San Antonio, the academic health center of The University of Texas at San Antonio (UT San Antonio), has announced a $6.5 million gift from San Antonio philanthropist Harvey E. Najim […]
The Email Of The Future In 1986
With so many online messaging services to choose from it’s almost as though the daddy of them all, email, has faded into the background as something you only use for more formal contacts. But…
iOS 26.6 adds new alert when you try blocking too many contacts
New beta software is here, and as discovered by Aaron Perris, a new alert appears in iOS 26.6 when you try to block one contact too many.
Here's how Pixel 11 Pro HiLight will work with Google Contacts
Pixel 11 Pro phones are getting a new "HiLight" notification system, and Google's Contacts app reveals how it will work.
Glyphosate: A story of science, risk, and nuance
In the summer of 2014, a California groundskeeper named Dewayne Johnson started noticing patches of raw, weeping skin spreading across his body. He had spent years applying Roundup, Monsanto’s glyphosate-based herbicide, for a school district, sometimes drenched in it when equipment malfunctioned. By 2014, he had a diagnosis: non-Hodgkin’s lymphoma. In 2018, a jury awarded him $289 million in damages, later reduced on appeal. Tens of thousands of lawsuits followed. The story hasn’t quieted down. It’s all over the internet, swinging between “this will kill you, buy organic” and “relax, you’re fear-mongering.” Some of that recent chatter stems from an Executive Order protecting glyphosate and its production, which set off intense infighting within the MAHA movement. Some of it reflects a deeper truth: Americans genuinely care about harmful chemicals in their environment (see poll below). And the conversation isn’t going anywhere, with a Supreme Court case involving Monsanto set for this April. Glyphosate (the active ingredient in Roundup) is one of the most widely used herbicides in the world. But does glyphosate cause cancer? And how much exposure is actually risky? With so much mistrust in institutions and corporations (and some genuine conflicts of interest), making sense of the actual scientific evidence is genuinely hard. Here is a translation of what the scientific evidence actually says. Does glyphosate cause harm? Glyphosate is an herbicide that kills most plants it contacts rather than targeting specific species. It works by blocking an enzyme pathway (EPSPS) that plants and many microorganisms need to produce essential amino acids. Without those amino acids, the plant can’t grow and dies. Glyphosate was first developed by Monsanto in the 1970s and became ubiquitous after the company introduced “Roundup Ready” crops in the 1990s. In 2024, Bayer removed glyphosate from residential Roundup-branded products due to litigation pressure. But today it is still the most widely used herbicide in the world. Farmers also discovered they could spray it directly on crops like oats, lentils, beans, and peas just before harvest to dry them out faster and make harvesting easier. Because of its widespread use, it’s obviously really important to understand if it’s harmful to humans. The key principle: The dose makes the poison The most important concept in toxicology is that “the dose makes the poison.” Sixteenth-century physician Paracelsus articulated what remains the foundational principle of toxicology: sola dosis facit venenum. Water will kill you if you drink enough of it. Aspirin saves lives at 81 milligrams and causes internal bleeding at higher chronic doses. So, at what dose is glyphosate poisonous? The LD50 in rats (the dose that kills half the test animals) is around 5,600 mg/kg body weight. Table salt is roughly 3,000 mg/kg. By that classic measure, glyphosate is less acutely toxic than salt. But some people are exposed to a lot of glyphosate through their work. And among the general public, there are many questions about low-dose, cumulative exposure from multiple sources over long periods. Does glyphosate cause health problems? Cancer Correlation maps are striking, with one analysis finding that 60% of counties that spray the most glyphosate have non-Hodgkin’s lymphoma rates above the national average. But correlation alone doesn’t establish cause, which is why animal and human studies matter. In animals: Rat studies are typically what most fear is rooted in, but most people don’t know the study details on the dosage given to rats. A pooled analysis of the 13 most rigorous rat studies found evidence that very high doses, around 55,000 times greater than typical food residue exposure, can cause certain cancers. In humans: One of the strongest studies followed 55,000 herbicide users over 20 years and found no overall increased cancer risk. There was one signal: among those with the highest use, rates of acute myeloid leukemia (AML) appeared elevated. A broader meta-analysis of 18 human studies also found no overall cancer risk, though a separate meta-analysis focused specifically on non-Hodgkin lymphoma found that people with high cumulative glyphosate exposure faced a 41% higher relative risk compared to those with low or no exposure. These human studies are observational studies (randomized controlled trials would be unethical), and meta-analyses are only as reliable as the studies they pool. But the story seems consistent: at very high exposure levels, there may be some cancer risk. But that’s about as far as the science currently takes us. Emerging research: gut and reproductive health Gut: Because glyphosate targets a pathway that exists in some gut bacteria, scientists have questioned whether it could affect the microbiome. In mice, a 2023 University of Iowa study found that glyphosate altered gut bacterial composition and raised markers of intestinal inflammation. A 2024 systematic review found similar patterns: disrupted gut bacteria and problems with the mucus layer that protects the intestinal wall in mice. Whether this translates to humans is an open question. The human gut is highly variable and resistant, and we don't yet have strong studies confirming the same effects in people. Reproductive health: Animal studies have found that glyphosate-based herbicides can interfere with reproductive hormones, including disrupting egg cell development in mice and reducing the number of eggs available in sheep’s ovaries. However, the doses used in these experiments were high, so it’s not yet clear whether the same effects would occur in humans. On the human side, a 2021 pilot study led by Mount Sinai researchers tested urine samples from pregnant women across the U.S. and found glyphosate in 95% of them. The study also found a possible connection between higher glyphosate exposure during pregnancy and a subtle physical difference measured in female newborns. That said, some connections weren’t statistically reliable and this was a small study. The researchers themselves said more and larger studies are needed before drawing firm conclusions. What do regulators say about glyphosate safety? In 2015, the International Agency for Research on Cancer (IARC), part of the World Health Organization, classified glyphosate as "probably carcinogenic to humans" (Group 2A). The classification is worth taking seriously. But, there’s an important distinction: IARC classifies hazard, meaning the potential to cause harm under some conditions. It does not assess risk, which accounts for actual exposure levels and the real-world probability of harm. The U.S. EPA, the European Food Safety Authority, Health Canada, and regulatory agencies in Australia and Japan have all concluded that glyphosate is “unlikely to be carcinogenic to humans” at realistic exposure levels. They’re asking a different question: given how much of this people actually encounter, what is the probability of harm? Your actual exposure is what determines your actual risk. What does glyphosate mean for your daily life? At the grocery store: Food residues are small. The EPA’s acceptable daily intake is 1.75 mg/kg of body weight per day. To hit that threshold from oatmeal alone, a 150-pound adult would need to eat roughly 50 pounds of oats every day. But this calculation addresses only one pathway (food), and we don’t yet have robust tools to measure people’s actual total exposure. If reducing exposure matters to you, organic certification prohibits synthetic herbicides, and organic oat products generally test at lower or undetectable levels. Either way, a diet rich in whole grains, conventional or organic, is far better for your health than one that omits them out of fear of residues. On the farm: Occupational exposure is orders of magnitude higher than consumer exposure. Farmers and farm workers who mix, load, and apply glyphosate-based herbicides, especially without protective equipment, face meaningfully different risk profiles. Proper PPE isn’t optional. Integrated weed management strategies that rotate chemical modes of action are also worth taking seriously, both for health and for long-term effectiveness. If you live near a farm: Spray drift is real. Concentrations near field edges can spike during and after application, particularly on windy days. This is an area where I think public health could really step up and empower rural communities with buffer zones, rather than placing the onus on individuals. But for now, knowing your local agricultural calendar and keeping windows closed during application are the first steps. Bottom line Dewayne Johnson was exposed to glyphosate at levels most people will never encounter, and a jury decided he deserved compensation. That outcome is not evidence that the oatmeal in your pantry is dangerous. But it is a reminder that the dose, the context, and the person doing the exposing all matter enormously. Glyphosate is a chemical tool with benefits, trade-offs, and genuine open scientific questions. Learning to hold that complexity without collapsing into panic or dismissal is, honestly, one of the most useful and hardest things to do in navigating modern health science. Love, YLE Your Local Epidemiologist (YLE) is founded and operated by Dr. Katelyn Jetelina, MPH PhD—an epidemiologist, wife, and mom of two little girls. Hannah Totte, MPH, is an epidemiologist and YLE Community Manager. YLE reaches more than 425,000 people in over 132 countries with one goal: “Translate” the ever-evolving public health science so that people will be well-equipped to make evidence-based decisions. This newsletter is free to everyone, thanks to the generous support of fellow YLE community members. To support the effort, subscribe or upgrade below: Subscribe
James Gibson and Cutter Leftwich Named to 247 Sports 30Under30 List
Kentucky football assistant coaches James Gibson and Cutter Leftwich were named to the 2026 edition of the 247 Sports’ 30Under30 List, recognizing the fastest-rising personnel and assistant coaches in college football. The list is in its 10th year and is compiled by a bevy of contacts across the industry.
Cortland County reports measles case; health officials track contacts, say public risk low
A person in Cortland County has been diagnosed with measles and is recovering at home, prompting local health officials to work to identify anyone who may have
Congo’s Ebola Footprint Widens as Officials Race to Gauge Epidemic’s True Scale
Congo’s Ebola outbreak is being detected across a widening swath of the country’s conflict-hit east as health authorities struggle to trace exposed contacts and determine the true scale of the epidemic.
Google's Phone app begins reverting one of its most controversial changes
The latest beta of the Phone by Google app brings the Contacts tab back to the bottom bar, less than a week after our exclusive report.
WHO joins Pre-COP31 to advance climate action that delivers for people’s health
The World Health Organization (WHO) is joining Pacific leaders, governments and partners at Pre-COP31 in Fiji from 5 to 8 October to advance health priorities in climate action and strengthen the Pacific voice ahead of the 31st Conference of the Parties (COP31) to the United Nations Framework Convention on Climate Change (UNFCCC).COP31, to be held next month in Antalya, Türkiye, marks an important step for global climate and health action. Health is one of the 10 priority themes of the COP31 Action Agenda, “Dynamic and Resilient Health Systems”, and a dedicated Health Day will take place on 9 November, the first day of COP31. The inclusion of health reflects growing global recognition that climate action and health are closely connected. The climate crisis is affecting population health globally. Across the WHO Western Pacific Region, which includes Pacific island countries and areas, the consequences of climate change include extreme heat, cyclones, floods, rising sea levels, food and water insecurity, infectious diseases and disruptions to essential health services. The Pacific in particular faces additional challenges. A recent review of 76 hospitals in 14 Pacific island countries found that 62% of health facilities are located within 500 metres of the sea or a river, leaving them particularly exposed to flooding, storm surges and sea-level rise.Bringing Pacific priorities to the global climate agendaThe Pacific Pre-COP31 provides an important opportunity for Pacific countries and partners to consolidate regional priorities and bring the experiences and leadership of Pacific communities into global climate discussions.Pacific countries have been advancing practical approaches to protect health in a changing climate, including strengthening climate-resilient health systems, improving preparedness for extreme weather events, building resilient health infrastructure and mobilizing climate finance for health. “This Pre-COP is an important moment for the Pacific, bringing global climate discussions to a region that has long been at the forefront of the climate crisis. It provides an opportunity for Pacific countries and areas to set their priorities, experiences and leadership on the global stage, and to ensure that the realities of Pacific communities are genuinely reflected in the decisions made on climate action,” said Dr Saia Ma’u Piukala, WHO Regional Director for the Western Pacific.Throughout this week, WHO will co-convene and participate in high-level discussions and events focused on climate and health, climate resilience, adaptation, financing and implementation. “Climate finance is essential for resilient and healthy Pacific communities,” emphasized Dr Mark Jacobs, WHO Representative to the South Pacific and Director of Pacific Technical Support. “We must ensure that financing reaches the people, communities and essential services most exposed to climate risks, supporting locally defined priorities and investments.”WHO will work with partners to strengthen the integration of health considerations across climate policies and investments, including national climate plans and resilience initiatives.Health as a driver of climate actionAmid the risks to health and pressures on health systems, well-strategized and implemented climate action can deliver significant health benefits. Investments in clean energy, sustainable transport, resilient infrastructure, food systems and nature-based solutions have proven to reduce health risks while contributing to climate mitigation and adaptation.“Climate action is truly an investment in health. Cleaner energy, healthier food systems and climate-resilient health services can protect lives while building stronger communities. We now need to turn these opportunities into action and make health a core part of climate investments,” said Dr Sandro Demaio, Director and Head of Office, WHO Asia-Pacific Centre for Environment and Health in the Western Pacific Region. “These benefits demonstrate that climate action is not only about reducing future risks. It is also an opportunity to improve lives today while building healthier, safer and more resilient societies.”At COP31 next month, WHO will also support the Health Pavilion, which will bring together the global health community and partners to advance health and equity within climate negotiations. With COP31 poised to move health higher on the global climate agenda, WHO will continue working with countries and partners across the Western Pacific Region and globally to strengthen climate-resilient and low-carbon health systems, and ensure that climate action protects and improves people’s health.____________________Media contactsElizabeth Bennett, WHO Asia-Pacific Centre for Environment and Health in the Western Pacific Region, elizabeth.bennett@who.intJulia Dongwhan Shin, WHO Asia-Pacific Centre for Environment and Health in the Western Pacific Region, dong.shin@who.intWHO Western Pacific Communications, wprocom@who.int
Google Contacts reveals what colors Pixel 11 HiLight will support
Ahead of the Pixel 11 launch, Google Contacts for Android has gained strings detailing upcoming support for HiLight.
College Student Is Disgusted By Her Roommate’s Science “Supplies,” So She Contacts The Landlord About The Disgusting Living Conditions
She never should’ve put it in the refrigerator in the first place.
Google’s September Pixel Drop upgrades VIP contacts, scam detection, and Pixel Watch
Google's September Pixel Drop makes VIP contacts one tap away.
Contacts are underway for friendlies with Brighton and Barcelona
Roma continues to finalize the program that will guide the team toward the 2026/2027 season. With the return to the Champions League and the centenary year just around the corner, the Giallorossi are ...
WhatsApp is launching parent-linked accounts for pre-teens
WhatsApp is rolling out parent-managed accounts for under-13 users, limiting features to messaging and calls while giving parents PIN-protected controls, alerts, and approval over contacts and groups.
Berlin businesswoman charged over alleged spying for Russia
Prosecutors say the Berlin marketing executive used her political and military contacts to help a Russian intelligence officer gain access to influential circles and seek information on German defense policy.
Google rolls out ‘Your info’ card in Contacts app on Android with phone number sharing [Gallery]
The Google Contacts app is making it a little bit easier to find your own number on Android, with a...
The September Pixel Drop improves the VIP contacts widget, adds Harry Potter themes
Audible just released Harry Potter: The Full-Cast Audio Editions audiobooks and Google is offering a free two-month trial to eligible users.
How To Set Up Your Emergency Contacts And Medical ID On Your iPhone
Take time to enable these features today before you need them; they could help save your life in an emergency.
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La Porte County Business Expo Brings Local Business Together September 17
Michigan City, IN – Businesses and community members from throughout La Porte County are invited to connect, discover local products and services, and build new contacts at the La Porte County Business Expo on Thursday, September 17, from 4:30 to 6:30 p.m. at Purdue Northwest – Westville campus. The collaborative event is hosted by the Michigan City Chamber, Westville Area Chamber, and La Porte Economic Advancement Partnership (LEAP) and will showcase businesses from across La Porte County and beyond. Attendees will have the opportunity to meet the people behind local businesses, learn about the products and services available and make
Ebola, chemical plants and health, hantavirus, common colds, heat and more
As they say, bugs have ears. Public health has had a relentless May. Chemical plant (near) explosions, Ebola, hantavirus, and that's before you even get to the usual suspects: common colds, heat, and ticks. Here’s an attempt to keep you up to speed and, more importantly, what it means for you and your community. But first, an announcement: World Cup The World Cup starts in 15 days (not like anyone is counting down), and we are hanging TVs in the Health Security Operations Center. It’s going to be a gorgeous, chaotic celebration of basically every culture on earth. And it’s going to take a team effort—from communities to individuals, from public health to health care—to keep people healthy. That’s where you come in. If you’re going to the games or live within 30 miles of a stadium, we would love to hear from you. Sign up for a weekly survey here. Thanks to the more than 1,280 people who have already signed up…you will be hearing from us soon!! Global disease “weather report” Hantavirus: Two more cases The global count of cruise ship passengers with hantavirus has now increased to 13 cases (11 confirmed), with three deaths. The two new cases are overseas and among people who were already quarantining: A crew member in the Netherlands. A Spanish national passenger who was quarantining at home tested positive through daily monitoring. They are now in a biocontainment unit. In the U.S., everyone remains negative. There may be more cases, given that the incubation period of hantavirus (the time from exposure to infection) is 45 days. But this week, we will reach a major milestone: the median incubation window is 18 days, and that will pass on May 29. What this means for you: Your risk from this cruise ship outbreak remains essentially nil at this point. Ebola rages on in Central Africa Big thanks to Dr. Craig Spencer, a humanitarian physician who has treated and survived Ebola, for jumping in to provide the YLE community with an update. Craig, take it from here… The combined confirmed and suspected Ebola cases in DRC are now more than 1,000. All signs are pointing to a very long and catastrophic outbreak in Central Africa: This is a vast undercount. We know this because the test positivity rate is hovering around 50%, only 20% of contacts are being traced (and in some areas, no contacts at all), and more cases keep popping up with no known connection. This all points to widespread and undetected community transmission. This is in only a week of detection. Compared to previous outbreaks, the growth is very fast, as the huge West Africa outbreak in 2016 was first detected at 49 cases and rose to 208 cases a month later. It took four months for that outbreak to reach the size of the current one in the DR Congo. The cases are spread out across 16 health zones. There are now multiple epicenters, making containment very difficult. Next door in Uganda, the case count is seven. While this number is low compared to DRC, a concerning development is that two health care workers recently tested positive with uncertain exposure histories. If they weren’t treating known Ebola cases, this means it’s spreading undetected in Uganda as well. On the ground, backlash, including the burning of health centers, has emerged, a pattern seen in nearly every outbreak and rooted in deep community distrust. It often stems from outside actors working in communities without fully understanding or addressing local priorities. Affected populations may recognize the severity of Ebola while still holding other concerns as more pressing, such as where their loved ones are buried. Community trust is essential to an effective response, but difficult to build during an active emergency. It is best established long before a crisis begins. U.S. priorities are made clear, and may backfire. The U.S. Administration has shown that its first priority is keeping Ebola out, with helping end the outbreak in the DRC a secondary concern. That's meant travel restrictions broader than anything we've imposed before — covering travelers from across the region, and reportedly some green card holders and permanent residents as well. For example, just these past two days, news broke that high-risk American travelers will be subject to a mandatory quarantine in Kenya before they are allowed to return. If an American is infected, the U.S. government plans to send them to a hospital it is standing up from scratch in Kenya. (Currently, Americans who were in the area are allowed to return but are diverted to three airports—Houston, Atlanta, and DC—for further screening.) Past administrations have used travel notices and stepped-up screening; this goes much further. At first blush, these strict precautions may sound prudent. But this approach could backfire in three ways: Restrictions this blunt give people every reason to hide where they’ve been and whom they’ve been near — making the people we most need to find harder to track, not easier. They also breed a false sense that this is someone else’s problem. But diseases are humbling. They find the small cracks in even the most impenetrable-seeming defenses. Lives lost. There is no treatment for this Ebola strain, which means survival depends heavily on the quality of the health system. We have that system in the States, but we are choosing not to use it for infected Americans. This is unbelievable and infuriating. (See a deeper dive from me here.) The only real way to lower the risk to Americans — and everyone else — is to end the outbreak in the DRC and across the region. What this means for you: If you have travel plans to this region, it’s time to cancel them. This is a high-risk situation in Central Africa, and CDC released a Level 4 Travel Advisory. There is also great uncertainty if and when the Administration will let you back in. To the general public in the U.S., your risk remains very, very low right now. U.S. disease “weather report” Ticks: past peak season? Good news, especially for people in the Northeast and Midwest: tick numbers continue to decline. Though we are at the peak of the season, this unusually early year is trending favorably. Heat-related illnesses in the North Heat risk is certainly not blanketing the entire country yet, but this week it will be moderate in the Midwest and the Southeast. What this means for you: Be sure to check the CDC HeatRisk tool. A red day isn’t the best day for that soccer game for a kid with asthma, and a stretch of orange days is a great time to check on your elderly neighbor. Common colds surging As far as respiratory viruses go, the only thing really going around right now is the common cold. It is higher this year than last year, but should peak very soon before returning this fall. Spotlight: Chemical plants Over the weekend, YLE California covered the serious situation that unfolded around a chemical plant in Orange County, California. Thankfully, the worst-case scenario (a chemical explosion) was mitigated, but only through luck. The health implications in a densely populated area could have been catastrophic. As the situation was winding down, another chemical explosion struck Washington State. This one was fatal. Health officials say the risk to surrounding residents from chemicals in the air and ground remains low, though the community deserves far greater clarity. Clean air and clean water consistently rank as Americans’ top public health concerns — yet when chemical disasters strike, communities are too often met with reassurances rather than transparency and accountability. Residents near the 2023 East Palestine, Ohio train derailment, for example, are still waiting to understand the long-term impact on their health, with few clear answers. What this means for you: Many are wondering if facilities processing potentially dangerous materials are in their neighborhoods. This interactive map allows you to enter your ZIP code and see all facilities monitored by the EPA, including any violations. Good news Ebola vaccines and treatment for the Bundibugyo species are in development. Two vaccine platforms are being explored, at least one of which may be deployable in as little as 2 months. One vaccine is being developed by Oxford, and the other uses the same biotechnology as the FDA-approved Zaire species of Ebola. (It may provide cross-protection, but it’s unclear at this point.) On the treatment side, two promising monoclonal antibody cocktails are likely to be deployed, though doses are limited and logistical hurdles remain significant challenges. Anni over at The Biotech Tea had a great explainer about the Ebola vaccine gap, if you want to read more. [ The Biotech Tea The Ebola vaccine gap, reading vessel damage, & the Makary exit 🗝️ Paid subscribers get the Biotech Term of the Week at $30/year (~$2.50/month). I try to keep it intentionally accessible, but if cost is ever a barrier, send me a message. A few people asked about expensing your subscription, so I put together a short email template… Read more 6 days ago · 10 likes · Annicka Evans, PhD ](https://www.thebiotechtea.com/p/the-ebola-vaccine-gap-reading-vessel?utm_source=substack&utm_campaign=post_embed&utm_medium=web) Polycystic ovary syndrome (PCOS) has been officially renamed polyendocrine metabolic ovarian syndrome (PMOS), following more than a decade of debate and input from roughly 22,000 clinicians, researchers, and patients worldwide. This is good because the old name was medically misleading, leading to patients without visible cysts being dismissed or overlooked entirely. The WHO estimates that 70% of people with the condition remain undiagnosed. A more accurate name should improve recognition, reduce stigma, and ultimately help the millions of people living with this condition get diagnosed and treated sooner. Poll Loading... Bottom line Public health situations are everywhere right now. Staying healthy takes public health professionals and systems working tirelessly behind the scenes and each of us showing up for our neighbors and communities. Love, YLE Big thanks to Ed Nirenberg for staying on top of the Ebola vaccines, Hannah Totte for all the figures, Dr. Craig Spencer for the Ebola insight, and Dr. Matt Willis for covering the chemical situation in CA. Your Local Epidemiologist (YLE) comprises a team of experts, ranging from physicians to immunologists to epidemiologists to nutritionists, working together with one goal: to “Translate” ever-evolving public health science so that people are well-equipped to make evidence-based decisions. YLE suite of newsletters reaches over 475,000 people across more than 132 countries. This newsletter is free to everyone, thanks to the generous support of fellow YLE community members. To support the effort, subscribe or upgrade below: Subscribe
How to share your estimated arrival time on iPhone and Android
ETA sharing on Apple Maps and Google Maps keeps contacts updated automatically while you drive safely. Learn step-by-step instructions for iPhone and Android.
Everything You Need to Know Before Installing the iOS 26.6 Update
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WHO Step-by-Step programme recognized as a promising innovation for mental health in humanitarian settings
WHO, in collaboration with the Pan American Health Organization (PAHO) and Lebanon’s National Mental Health Programme, showcased Step-by-Step at the World Bank Group’s biennial Fragility Forum in Washington, DC. The forum convened more than 1500 representatives from governments, international organizations and civil society to advance the development agenda in the world’s most fragile and crisis-affected communities. WHO was invited to demonstrate Step-by-Step – a digital self-help intervention for depression, alongside innovations presented by Stanford University and Google. The World Bank Group selected Step-by-Step from among more than 50 innovations that they reviewed in the lead up to the Forum.About Step-by-StepStep-by-Step is a free digital tool developed by WHO in collaboration with Lebanon’s National Mental Health Programme and other partners, that helps people manage depression and anxiety on their own, with light guidance from a trained supporter. It uses a picture-based story to walk users through evidence-based techniques for managing common mental health conditions. Users complete five modules, with weekly contacts – of around 15 minutes each – from a trained non-specialist helper, such as a community health worker.Evidence-basedClinical trials in Lebanon involving nearly 1250 participants – including 680 Lebanese participants and 569 Syrian participants – showed that Step-by-Step significantly reduced depression, anxiety and stress, and improved daily functioning. By the end of the programme, a reduction in depressive symptoms of more than 50% was reported by almost half (46%) of Lebanese participants and more than one third (37%) of Syrian participants compared to approximately 14% of those who did not use the programme. Cost-effectiveness analyses further suggest that Step-by-Step may offer a cost-saving response to depression in humanitarian emergencies in low- and middle-income countries.Used globallyStep-by-Step is already in use nationwide in Lebanon and Thailand, as part of each country’s mental health system. In India, the NGO – Kaya Guides – has adapted Step-by-Step for delivery through a widely used messaging app. Together, these programmes have provided thousands of people with evidence-based support for depression. The content is freely available from the WHO website for any organization or country to adapt for their own context.A new implementation guideThe Fragility Forum coincided with the recent launch of WHO’s new practical guide: Psychological self-help interventions: delivering self-help for individuals, featuring Step-by-Step and Doing What Matters in Times of Stress (WHO, 2026). The guide is designed to help governments, health workers, organizations and planners bring evidence-based mental health support to more people, particularly in low-resource and crisis-affected settings.
Maryland declares measles outbreak in 3 counties
The Maryland Department of Health has declared a measles outbreak in St. Mary’s, Carroll and Cecil counties, health officials said Monday. The health department said it is investigating 14 confirmed cases among unvaccinated Maryland residents and that most of the case contacts occurred within specific households. Measles is considered highly contagious and can be spread through the air when an…
Trump administration settles lawsuit with ex-Trump adviser Carter Page
The Justice Department has reached a settlement in a lawsuit brought by former Trump campaign adviser Carter Page, who sued the DOJ and FBI for over flawed government surveillance he faced due to his Russian contacts in 2016, according to a filing with the Supreme Court Wednesday.
Senator contacts leagues over 'gambling's ugly takeover'
As prediction markets expand partnerships with major U.S. sports leagues, a U.S. senator sent letters to six league commissioners Thursday raising concerns about "gambling's ugly takeover of sports."
Tuberculosis policy should shift focus to population-level interventions for greatest impact
Nature Health - Interventions to improve tuberculosis care for those who already seek it or their household contacts will have limited impact on the tuberculosis epidemic, whereas strategies to...
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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2026 Best of Business
WBJ’s Best of Business awards are centered around one concept: referrals. Businesses will attract and retain new customers in all sorts of ways, but most will tell you the best way is to get your existing clients to do it for you. A recommendation from a trusted source goes a long way whenever a company leader is looking for a lawyer, an accountant, a place for lunch, a venue for a large event, or a fun place to take employees as a reward for all their hard work. Now in its 13th year, WBJ’s Best of Business awards are essentially recommendations from trusted sources for the organizations to best help your companies succeed. As we do every year, WBJ compiled this list of winners by asking our readers to vote in the various categories. From Nov. 1-28, more than 2,160 votes were cast. The top votegetters are the winners of this year’s 54 categories. To celebrate these winners and to meet the best of the best, I invite you to attend WBJ’s Best of Business awards event at 4:30 p.m. on Jan. 28 at the Beechwood Hotel in Worcester. Part celebration and part hyperactive networking event, the Best of Business awards is a unique experience in the local economic scene. Always a good time, the room is full of potential contacts, who can all help your business achieve that next level of excellence. You can register here. – Brad Kane, editor
Android’s upcoming ‘Tap to Share’ can send contacts, files, etc – here’s what it looks like [Gallery]
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Hantavirus cruise LIVE: World Health Organization hosts briefing as authorities race to track contacts from cruise ship infections
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Denver’s STAR program reduces police contacts and arrests, but can’t meet demand
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Don’t miss out on the latest science in JCSM
The Journal of Clinical Sleep Medicine is moving to Springer Nature. View new articles in Volume 22 on the Springer website. Logging in as an AASM member AASM members have full access to all JCSM content. Follow these steps to log into the new website as a member: Go to the new journal website homepage: https://link.springer.com/journal/44470/ Scroll down and look for the “Sign in through society site” button. This button will take you to the AASM log-in screen and redirect you back to the journal website. Monthly new content alerts If you’ve previously opted in to new issue alerts for JCSM, you’ve been registered to receive monthly new content alerts from Springer Nature for JCSM. These alerts ensure you’ll never miss out on the latest science published in JCSM. To make sure delivery of the alerts is seamless, please add “Springer Alert TOCalert@springernature.com” to your contacts.
Roundup: ChatGPT / GM engine failures / US business activity surges
Convenience meets risk: OpenAI has added a ChatGPT feature that can search, analyze, draft and send messages through Apple’s Messages app on Macs, making it easier to manage conversations and automate tasks. While convenient for personal and business use, the integration requires expanded access to contacts and computer data, raising concerns about sensitive information being […]
WhatsApp adds Apple CarPlay and Android Auto upgrades, iPad sign-ups, and more
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Ukraine’s Academy of Sciences warns against Russian cooperation after attack
The National Academy of Sciences of Ukraine has urged the international scientific community not to “restore or legitimise institutional cooperation with Russian state scientific and educational structures,” after a Russian drone hit its Presidium building in central Kyiv, killing at least two people and injuring several others. The drone strike took place in the early afternoon on September 28 while staff were working.The academy called the strike, one of several Russian attacks on Ukraine’s capital using jet-powered drones in recent days, an act of terrorism. “It is a strike [. . .] on the very idea that knowledge, research, and the search for truth should serve life, not its destruction,” it said in a statement.The academy thanked the global scientific community for its solidarity following the attack and warned against any temptation to normalise scientific relations with Russia.“Science cannot exist outside of moral responsibility. There can be no ‘ordinary scientific cooperation’ with a state that kills people and destroys scientific institutions of another country,” it said.“We urge not to create opportunities for Russian state institutions to return to the international scientific community as if nothing happened. There can be no ‘science beyond politics’ when science is attacked with weapons.”After the full-scale invasion of Ukraine in 2022, Europe almost entirely cut institutional ties and joint programmes with Russian science, although personal academic contacts are still ongoing.Related articlesRussia widens targeting of European research centresHow geopolitical rifts cut scientific collaborationThe European Federation of Academies of Sciences and Humanities (ALLEA), for instance, continues to exclude the Russian Academy of Sciences from its network.ALLEA condemned the latest attack as a “barbaric act” and part of a broader “systematic targeting of Ukraine’s scientific and cultural infrastructure.” This is a “deliberate attempt to erase the conditions under which free inquiry, knowledge, and democratic life are possible,” it said in a statement.Since Russia’s full-scale invasion, more than 4,650 educational institutions across Ukraine have been damaged, and a further 423 have been destroyed, according to ALLEA.National academies across Europe joined ALLEA in condemning the attack. “Science is about the pursuit of knowledge for the benefit of humanity, so this is an attack on civilisation itself,” said Paul Nurse, president of the UK’s Royal Society.Attacks on scientific, university and cultural institutions “are attacks on the foundations of society and constitute a clear violation of international law,” wrote the German National Academy of Sciences Leopoldina.The presidents of the US National Academies of Sciences, Engineering and Medicine also released a joint statement condemning the attack and pledging to continue to support the Ukrainian research community.The targeting of the Ukrainian academy prompted outcry from European leaders. “Today, science became a target for Russia,” European Commission President Ursula von der Leyen wrote on social media.“These strikes are the latest illustration of the Russian regime’s hostile contempt for science and truth,” said French President Emmanuel Macron.
A new Android 17 beta reveals plans for “Pixel Glow” light animations.
Google just released the fourth beta for Android 17 today, and now, 9to5Google and Android Authority point out that it contains mentions of a new lighting feature that we might see on the next round of Pixel phones. The Pixel Glow details say it “uses subtle light and color on the back of your device to inform you of important activity when it’s face down,” when interacting with Gemini, or when favorite contacts are calling. [Link: Pixel Glow 'visual feedback' tool might just hint at big Pixel 11 hardware changes | https://www.androidauthority.com/pixel-glow-3658443/ | Android Authority]
Congo Reopens Main Airport in Ebola Epicenter as Officials Brace for Long Outbreak
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Science diplomacy lessons from a North Korean volcano
Mount Paektu, a mythic, active volcano on the border between North Korea and China, is almost the epitome of a scientific challenge that crosses political lines. In 946 CE, it erupted in one of the five biggest volcanic events of the past 10,000 years, kicking up huge quantities of ash and sending destructive mud flows down river channels for hundreds of kilometres. Should this happen again, the entire region, including easternmost Russia, South Korea and even Japan could be hit. “It’s definitely got the potential to be big,” said James Hammond, a professor of geophysics at Birkbeck, University of London. An eruption on the scale of 946 would have “huge regional impact.” For the past 15 years, Hammond has helped lead a groundbreaking collaboration with North Korean scientists to study the volcano, navigating scientific sanctions, tough export controls on scientific equipment and a long, pandemic-enforced exodus from the country. Although he seems more at home on far-flung research expeditions – before speaking to Science|Business, Hammond was camping out on a Greenland ice sheet – he has also advised the European Commission on its changing science diplomacy strategy. His long experience with North Korea has made Hammond sceptical of blanket bans on science collaboration, no matter the country.This is a live question in Europe, where in the wake of Russia’s 2022 invasion of Ukraine, institutional ties with Russian universities were almost entirely severed, although some scientists fear this could undermine our understanding of climate change’s impact on the Arctic. Here, Hammond tells the story of the Mount Paektu mission and the policy lessons he takes from it. Ominous rumblingsThe genesis of Hammond’s collaboration came in 2002, when Mount Paektu began to rumble ominously. Earthquake activity picked up and the volcano began to emit unusual gases. North Korean scientists took notice. “People felt we need to know more about this volcano,” said Hammond. In 2011, North Korean vulcanologists put out a request for international expertise to help them learn more. At the time, Hammond and his collaborator, Clive Oppenheimer, were working on a vulcanology project in another sanctioned country, Eritrea, and so decided to answer the call. Within a month, they had flown into Pyongyang. “It was pretty incredible,” recalls Hammond (left). “We were made to feel like honoured guests, and invited to official celebrations.” The scientific opportunity was huge. Paektu is unusually positioned, a thousand kilometres from where tectonic plates rub against each other in the Pacific. “It was an incredibly interesting volcano, but not much research had been done, at least not in the international community,” he said. “There was so much we felt we could do. And we had these partners that were super keen to engage.”The mission received an unusual visitor in the form of volcano-obsessed filmmaker Werner Herzog, who accompanied Hammond and Oppenheimer while directing his 2016 film Into the Inferno about volcanos across the world. Four days into the trip, the German director delivered a long speech about reunification to his North Korean hosts, recalls Hammond. “He got to the heart of the Koreans and how they felt, and how they thought, in a way that I'm not sure I ever will,” he said. UN sanctionsHowever, Hammond realised he’d been “naïve” about how difficult it would be to collaborate with North Korea, which was sanctioned far more heavily than Eritrea. “We didn’t fully appreciate the all-encompassing nature of restrictions,” he said. In 2016, as tensions escalated over Pyongyang’s nuclear tests, a United Nations resolution banned all joint scientific work with North Korea. However, the UN sanctions did allow countries to request carve outs, and the UK successfully requested an exemption for Hammond’s work. Related articlesEU pushes for joint science diplomacy, but care needed to avoid gridlock, experts sayRussia severs its last ties with German scienceAnchor Greenlanders in Arctic climate research, experts tell EU ahead of policy updateExport controls have also delayed Hammond’s work. In one case, it took 18 months to get approval from the UK government to take seismometers, which measure earthquakes, to North Korea. “It was frustrating,” he said. “But they didn’t just say no.” However, one instrument, called an induction coil, used to measure how the earth conducts electricity, was blocked entirely because it can in theory be used to detect submarines. Karaoke bondingSince the collaboration started in 2011, Hammond has visited the country around 15 times, although the pandemic closed off North Korea for more than five years. A trip last November was Hammond’s first since the outbreak. Despite this lengthy interlude, Hammond has deep bonds in the country. The North Korean scientists Hammond works with are somewhat isolated, as they struggle to access the latest research papers and travel to international conferences. That said, they are “excellent geophysicists” and are “very well trained in the field,” he said. Over karaoke and chats about their families, “we’ve made friendships, for sure,” he said. The authorities have to sign-off things like the placement of seismometers, for example, but Hammond said these requests have been approved. “Everything that we've asked for within a scientific context has been delivered.”Scientific backchannels? These kind of personal links between scientists across political lines are one purported benefit of science diplomacy. During the Cold War, some historians argue, scientific contact between the US and Soviet Union laid a groundwork of trust for other cooperation, such as on arms control. Hammond agrees that backchannel contacts to North Korean geophysicists are hardly likely to defuse a military crisis on the Korean peninsula, but the simple fact of the scientific collaboration makes contacts between diplomats that little bit easier. “It creates opportunities to understand each other a little bit better,” he said. “When maybe you have those more difficult discussions as diplomats, it's coming from a slightly better place.” Cutting tiesDrawing lessons from the Mount Paektu mission for today’s links with Russian science isn’t simple. The analogy is far from exact, Hammond said, “because one is essentially a Cold War, versus a pretty hot war in the case of Russia.” But Hammond’s broader argument is that the challenges we face, such as climate change, pandemics, biodiversity loss, pollution and so on, have globalised in an unprecedented way, making blanket shutdowns in collaboration with any country unwise.He’s somewhat critical of the UN scientific sanctions imposed on North Korea in 2016, even though they did allow for exceptions. “I think a blanket halt to some of these things, when we face big global challenges [. . .] that’s quite a risky thing to do,” he said.Institutional endorsement?European academics are still by and large free to work individually with Russian counterparts. However, official, institutional partnerships have largely ended. Shortly following the full-scale invasion of Ukraine in 2022, Russian university rectors wrote a public letter endorsing the war, meaning European universities fear official collaboration could also be seen as a kind of endorsement. Hammond acknowledges there is a risk of legitimising regimes, and state-controlled universities, through scientific cooperation. “That’s the trade off you have to make,” he said. Strategic projectsWith Russia, instead of giving a green light to restart all Arctic science, a middle ground might be firing up a few carefully selected “strategic” projects, said Hammond. After all, European countries are still collaborating with Russia on the International Thermonuclear Experimental Reactor, an experimental nuclear fusion plant in the south of France. However, even if Europe did try to revive Arctic science with Russia, there’s no guarantee Russian scientists would play ball. A series of high-profile arrests of physicists in Russia accused of sharing their findings with the outside world has made collaboration fraught. Even before the invasion of 2022, “the Russian regime made it increasingly difficult, and this sort of discouraged people,” Dag Rune Olsen, rector of the Arctic University of Norway, told Science|Business last year.
Rabid skunk found in Arvada; health officials urge caution during warm winter
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WeChat Zero-Click Worm Took Over Accounts on iPhone and Android via Incoming Calls
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Liverpool's ahead-of-the-curve approach to youth recruitment
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Asking Eric: Youth podcaster ghosted by professional contacts
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Roma Taking an Extended Look at Free Agent Defender
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Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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