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Dr. Bucan-Kurepa prescribes a more personal approach to healthcare - Cross Timbers Gazette | Southern Denton County | Flower Mound
After 27 years of practicing medicine in Flower Mound, it would be easy to assume that Dr. Jelena Bucan-Kurepa has developed quite a following that has created a loaded daily schedule with a seemingly endless number of patients. But it’s actually quite the opposite. Sure, she has a devoted following of families who trust her […]
Devontez Walker fully practices Thursday
Ravens WR Devontez Walker seems on track to make season debut
Iowa shows healthcare reform is possible
Iowa has shown that reform is possible. We should build on that progress so more of our health care dollars, and more of our physicians' time, are devoted to what
Eagles Rule Out DeVonta Smith, Zack Baun for Game vs. Rams
Philadelphia will be down a couple of key contributors for an important game.
Reimagining how scientists study the chemistry of the air
Professor Victoria Barber and doctoral student Cooper Crabtree are spearheading Keck Foundation-funded project charting a path toward better understanding atmospheric oxidation. by Álvaro Castillo, UCLA College of Letters and Science From the vantage point of Victoria Barber, a UCLA assistant professor of chemistry and biochemistry, understanding the chemical reactions that shape air quality and climate are among the most pressing scientific challenges of our time. And thanks to a recent grant from the W.M. Keck Foundation, she and doctoral student Cooper Crabtree will spearhead a new research project exploring exactly how pollutants form in the atmosphere. Specifically, the project will examine how volatile organic compounds transform through atmospheric oxidation and explore how pollutants, like smog, form in the atmosphere. VOCs are released by sources ranging from trees and wildfires to vehicle exhaust pipes and consumer products such as cologne and perfume. As they undergo atmospheric oxidation, they can transform into a wide range of other compounds. Anyone in Southern California can attest to the urgency of this area of research — for example, in late July of this year, Los Angeles County was under an active ozone pollution advisory for almost a full week. While many people associate ozone with the protective ozone layer high in the stratosphere, ground-level or tropospheric ozone is a harmful secondary pollutant formed through atmospheric oxidation. Understanding how VOCs transform into pollutants like ozone is therefore critical to improving air-quality forecasts and informing strategies to reduce exposure. “My group is focused on trying accelerate our understanding of these networks of reactions so that we can do a better job of predicting how those pollutants form,” Barber said. “When we make decisions about how we might alter emissions, we can understand how that’s going to influence the production of these downstream pollutants.” With support from the W. M. Keck Foundation, Barber and Crabtree are developing new experimental approaches that will combine — and improve — techniques to study hundreds of chemical systems more efficiently than traditional methods allow. Instead of spending years decoding a single VOC, the project seeks to dramatically expand the pace and scale of discovery. The grant comes at a particularly important moment for environmental research. Barber, who joined UCLA in 2023, says funding for climate and air-quality research, especially for early career scientists, has become increasingly difficult to secure, a challenge compounded for ambitious projects that require building entirely new research infrastructure. The Keck Foundation’s support, Barber said, provides the flexibility to pursue bold early-stage, high-risk ideas that may be more difficult to fund using conventional federal funding sources. “It’s really, really hard to do environmental research under the current federal paradigm,” Barber said. “By stepping in and providing stable and flexible funding to explore this new idea, the Keck Foundation is making a huge difference to my research program.” In addition to funding early-career faculty, the Keck Foundation’s support is also focused on empowering graduate students like Crabtree in their scientific growth. The project gives Crabtree the opportunity to help develop an entirely new experimental approach to studying atmospheric chemistry — an experience that will provide him with valuable technical skills, scientific training and preparation for the next stage of his career. Stable funding also allows doctoral students like Crabtree to devote themselves more fully to research rather than balancing their scientific work with additional teaching responsibilities needed to cover funding gaps. “Getting to devote more of my time to research this past school year has greatly improved the pace and quality of our experiments, data analysis and planning for our future work,” said Crabtree, who is pursuing a Ph.D. in chemistry. “I feel very lucky — especially amid the current uncertainty surrounding scientific funding — to be able to continue exploring exciting knowledge gaps in our field and growing as a scientific researcher.” For Barber, mentorship is among the most rewarding and important aspects of her role as a faculty member. “Our jobs as faculty are to do good science and make good scientists,” she said. “I believe the Keck Foundation shares this belief and sees the potential positive impact this project can have.”
BALL x PIT expansion ‘Risen Ballbylon’ announced
Publisher Devolver Digital and developer Kenny Sun have announced BALL x PIT expansion “Risen Ballbylon.” It will launch on November 6 for $6.99.
JRR Tolkien to join CS Lewis in Westminster Abbey’s Poets’ Corner
J R R Tolkien, the devout Catholic author whose Christian beliefs helped shape The Hobbit and The Lord of the Rings, will be honored with a memorial in Westminster Abbey s Poets Corner alongside his
Venus May Have Devoured Its Moon, Scientists Find
Scientists suggest that Venus did indeed once have a moon, which spiraled inwards until it crashed into the planet's surface.
Seahawks corner Devon Witherspoon signs. Will Christian Gonzalez be next?
Per reports, Devon Witherspoon agreed to a deal that makes him the NFL's highest paid corner. Might that set the stage for Christian Gonzalez?
DeVonta Smith back at practice for Eagles
The Eagles welcomed a key part of their offense back to the practice field on Monday.
DeVonta Smith not practicing
Hamstring injury prevents Philadelphia Eagles WR DeVonta Smith from practicing
No practice for DeVonta Smith Wednesday
Eagles WR DeVonta Smith sits out practice Wednesday because of injury
Devon Witherspoon, Seahawks agree to four-year extension
New Permanent Alchemy Exhibit in Philadelphia Reveals How Art and Chemistry Intertwine
Philadelphia has quietly been sitting on what the Science History Institute says may be the finest collection of alchemical fine art in the world. Now, for the first time, visitors can see that collection in a permanent exhibition. Fire and Gold: The Art of Alchemy, 1450–1850 is the Science History Institute’s first permanent display devoted […]
Patriots make Christian Gonzalez the NFL's highest-paid cornerback, AP sources say
Christian Gonzalez has agreed to a four-year, $135 million contract with the New England Patriots that makes him the highest-paid cornerback in NFL history, two people with knowledge of the deal told The Associated Press on Tuesday. One of the people said Gonzalez is getting $102 million guaranteed. Gonzalez surpassed Devon Witherspoon's new contract from the Seattle Seahawks.
Devonian Health Group Inc. Anticipates to Commence Trading on the NYSE American
/PRNewswire/ -- Devonian Health Group Inc. ("Devonian" or the "Company") (TSXV: GSD) (OTCQB: DVHGF) is pleased to announce that in connection with an...
Devon Dampier Is the Utah Problem Arkansas Must Solve
Utah quarterback Devon Dampier is more than a dual-threat quarterback. He is the central stress point in an offense that can punish Arkansas for losing leverage, missing tackles, or allowing one broken play to become a touchdown. Devon Dampier Is the Utah Problem Arkansas Must Solve Arkansas is not traveling to Salt Lake City simply …
Devon health maternity unit closure is 'a catastrophic failure'
County councillors discuss the closure of the maternity unit in North Devon District Hospital.
UL System schools share team-level revenue sharing budgets despite new state law
Louisiana Tech University will spend nearly $2 million in public money to pay its student-athletes this year, while the University of Louisiana at Lafayette will devote $1.5 million to its sports teams.
Ministers explore how to stop regional leaders misusing planned new spending powers
Labour wants to make sure mayors and council chiefs in England can be held to account for extra revenues devolved to them
Can a civility pledge help address our toxic politics?
By Vince Bzdek It has been a tale of two cities in Colorado Springs in recent weeks. On Sept. 17, a nine-hour-long city council meeting on the merits of the Project Taurus data center devolved into violence when Colorado Springs Police brawled with several audience members after two men tried to shield a woman who […]
Ben Affleck shares rare insight into coparenting dynamic with Jennifer Garner: ‘I’m really, really grateful’
Ben Affleck reveals that he and ex Jennifer Garner have a ‘really wonderful’ coparenting dynamic, and devote their energies toward their three children.
Democrat Manny Rutinel resigns from state House to focus on competitive race in Colorado’s 8th Congressional District
Democratic Rep. Manny Rutinel resigned from the state legislature Friday to devote his full attention to his campaign in Colorado’s 8th Congressional District, where he is challenging Republican U.S. Rep. Gabe Evans. The open seat in House District 32 will be filled by a vacancy committee. The Adams County Democratic Party has not responded to […]
Brazil: Lessons from a Disaster
By Antonio Martins (Outras Palavras) Defeats become deeper and more prolonged when we misunderstand what caused them, avoid correcting course, and embrace “solutions” that only compound our mistakes. Lula’s government and the Brazilian left suffered a disaster in Sunday’s election. Contrary to every poll, the president finished the first round 2.2 million votes behind Flávio Bolsonaro—and, more significantly, 3.4 million votes below his total four years ago, when the machinery of the state was working against him and in favor of his opponent. His vote share declined in 98 percent of Brazil’s municipalities. The PL, the main party of the far right, elected 121 deputies and 28 senators, becoming the largest caucus in both houses of Congress. The parties aligned with the Centrão—Brazil’s bloc of transactional center-right parties—were somewhat diminished, but will still hold roughly 250 seats in the Chamber of Deputies and 35 in the Senate. That will make it easier to assemble the majorities needed to amend the Constitution or impeach Supreme Federal Court justices. If elected, Flávio Bolsonaro could appoint four members of the Court, substantially altering its internal balance of power. What produced these results? How can the far right be prevented from consolidating them into a prolonged political hegemony? And what is the essential change of direction the left now needs? Explaining the Disaster Across the commercial media and the exuberant chaos of digital platforms, interpretations are multiplying. Some focus on specific episodes: Lula’s absence from the Globo debate, his very close relationship with Alexandre de Moraes, or his emphasis on issues supposedly remote from most people’s everyday concerns, such as rare earth minerals. Among the more systemic interpretations, three seem especially questionable. One argues that the principal defeat was not the left’s, since its congressional representation declined only slightly. The decisive movement captured at the ballot box, according to this view, was a shift within the right itself—from the more moderate and transactional forces of the Centrão toward the more ideological and radicalized forces of the PL and Novo. A second interpretation holds that the nature of electoral and political processes has changed. The material interests and aspirations of society, it argues, no longer play the central role they once did; they have given way to forms of subjective self-identification that the left has yet to understand. And a third concludes that, because of these two developments, we should expect a political winter: a prolonged period in which the far right and the broader right dominate Brazilian political life. There are important elements in all three interpretations. The problem lies in what they deny or leave out: Lula’s third government was a small-bore government. It offered the majorities that elected it neither a clearly better life nor reasons to believe again in politics and its power to transform society. These failures flowed from two fatal accommodations, which I will examine below. As a result, the government suffered a slow but steady erosion of support. And, as has happened in so many Western countries, it gave the far right the opportunity to present itself as anti-system and to benefit from popular frustration and distress. The interpretation that emphasizes the migration of votes from the center-right and traditional right toward the far right has been advanced, among others, by the courageous journalist Leonardo Sakamoto. In his UOL column on Monday, October 5, he highlights the miserable behavior of the traditional conservative parties. Over the past four years, they repeatedly joined forces with the “neo”-fascists, helping to “normalize” them—a criticism that could equally be directed at almost the entire corporate media. Believing they could use the far right as a stepping stone, they instead ended up partly devoured by it. This was especially true in the Senate, where the PL’s gain of 13 senators and Novo’s gain of two came at the expense of the PSD, which lost nine; the MDB, which lost two; the PSDB, which lost two; and the PP, which lost one. Sakamoto’s observation is accurate and necessary, but it leaves uncomfortable questions unanswered. Why did the erosion of the Centrão benefit the far right rather than, for example, producing growth for the left—as has happened so many times before, both in Brazil and elsewhere? The answer is not difficult. Throughout its four years in office, Lula’s third government was almost invariably associated with the Centrão. Here lies its first accommodation: accepting the limits imposed by conservative institutions; avoiding, as much as possible, any attempt to strain those limits through popular pressure; and believing only in the modest changes that could be squeezed through openings in Congress. The failure of the campaign to end the six-day workweek is emblematic. Lula could have electrified the presidential race by pairing it with a popular campaign for passage of the measure. Instead, he chose to place his hopes in the hands of Senate president Rodrigo Alcolumbre. He generated no mass mobilization, did not force his opponents onto an uncomfortable defensive, and won no victory. In September 2025, the government squandered the greatest of its many opportunities to shake up conservative power in Congress. Popular opposition to the so-called Shielding Amendment—which, if approved, would have restricted criminal proceedings against members of Congress—brought crowds into the streets, mobilized primarily by artists and social movements. This opened the possibility for a broader political education: a campaign that could begin exposing the limits and dysfunctions of Brazil’s political system while putting Bolsonaro’s movement on the defensive for its predictable support of political privilege. The amendment was defeated. But the executive branch then backed away from the fight. It remained associated with an institutional world widely seen as corrupt, elitist, and indifferent to ordinary people’s struggles. In doing so, it forfeited its credibility as a vehicle for the protest vote. On Sunday, it reaped the bitter fruits. Are We Doomed? Taking a different approach from Sakamoto, the philosopher Moysés Pinto Neto and other writers have drawn attention, in their first analyses of October 4, to the fragmentation of the public sphere produced by Big Tech platforms. Through their algorithms, these platforms present each person with a different view of social reality. As a consequence, it becomes much harder to identify common material problems and demands—for example, the fight for labor rights or for a properly funded public health system. Voters no longer embrace such demands, these authors argue, because they no longer see themselves as part of a collective. Instead, they tend to value the identities assigned to them by neoliberal subjectivity—the role of the entrepreneur, for example. On this interpretation, the left’s possible error lies in clinging to outdated illusions. Moysés’s warning is highly relevant and resonates with arguments such as Naomi Klein and Astra Taylor’s “Apocalyptic Fascism and the Billionaires’ Bet.” Unlike a century ago, the far right no longer promises a radiant future. It concentrates instead on resentment—especially that of young men. “They belong to a generation that fears it may never own a home, but compensates with the pleasure it gets from constantly provoking progressives online. Convinced their future has been stolen, they share memes romanticizing historical authoritarian regimes,” the authors write. But Moysés seems to confuse this danger with inevitability. He fails to see that the left’s answer cannot be adaptation. On the contrary, it must strengthen the possibility of politics as collective action. Nor does he recognize that precisely such a reversal is already becoming possible in some of the most promising mobilizations of the twenty-first century: the election, at the end of 2025, of the young Muslim Zohran Mamdani as mayor of New York, on a platform centered on the intensely material fight for an affordable city; the Left Party’s victory in Berlin two weeks ago, built around the demand to expropriate private real-estate corporations; and the very recent wave of demonstrations in Spain—including an occupation of Madrid’s Puerta del Sol—in which tens of thousands of young people mobilized by the Tenants’ Union have demanded limits on rents. By putting itself in the straitjacket of the “fiscal framework” in the first months of 2022, Lula’s third government adopted the second fatal accommodation of its term. Faced with conservative institutions and a country devastated by four years of Bolsonaro, increased public investment was the government’s remaining weapon for offering a more dignified life to the majority and forging an anti-conservative pact with them. The same state that disburses 1 trillion reais a year to enrich a small class of rentiers could instead spend money to extend the Family Health Strategy to every Brazilian, at a cost of 30 billion reais; provide full-day public schooling and childcare to all adolescents and children—and, especially, relief to their mothers; achieve universal sanitation while cleaning up polluted urban rivers; multiply metro systems; begin transforming the urban peripheries; and undertake many other urgently needed projects. In April 2023, an article in Outras Palavras warned that the fiscal framework could “shrink the Lula government and preserve the forces that condemn the country to inequality and regression.” A year later, another article showed that restraints on public spending were strangling policies vital to ordinary people and undermining the president’s popularity. In November 2024 came a reality check, in the form of the government’s humiliating defeat in the municipal elections. Even then, the fiscal lock was neither removed nor loosened. On the contrary: throughout the government’s four years, fiscal restraint remained central to its political narrative. The administration proudly proclaimed that it had “put the state’s accounts in order,” without grasping either how misleading that phrase was—given the payment of 1 trillion reais in interest—or how badly the message was hurting it politically. Lula finally woke up in September 2026. The increase in Bolsa Família benefits, after four years of being frozen; the announcement that anti-obesity drugs would be offered through Brazil’s public health system; and the ban on online betting showed that the state has the power to act decisively on behalf of the majority when those in government are willing to confront obstacles. The huge marches that closed the campaign in Fortaleza, Salvador, Rio de Janeiro, and São Paulo on the eve of October 4 showed how such initiatives can mobilize activists and the broader public. But it was too late—and too little to change the outcome of the first round. History has not ended The possibility of a turnaround in the three weeks leading up to November 25 cannot be ruled out. It will not be simple or easy. Lula must not only make up a deficit of 2.2 million votes; he must also offset the movement of voters who backed other right-wing candidates in the first round, most of whom are likely to move toward Flávio Bolsonaro. Pulling that off will require a broad, grassroots effort to win over voters, potentially reinforced by new initiatives from Lula. The coming hours and days will be decisive. If Bolsonaro’s movement also wins the presidency, the result will create a high-risk situation for Brazilian sovereignty and democracy. The enormous challenges posed by such an outcome would require the left to reexamine, in depth and with a genuine willingness to engage in self-criticism, its political projects—or its lack of them—and its practices. But would that mean we are condemned to the long winter of far-right hegemony that some analyses are beginning to forecast? It is far too early to say, suggests a recent text by Álvaro García Linera, the thinker who served as vice president of Bolivia under Evo Morales. His central hypothesis is that this political current will prove short-lived. At a moment when the entire world is once again talking about sovereignty and protecting national economies, the far right offers a stale, recolonizing neoliberalism. Its submission to the United States is as blatant and pathetic as Flávio and Eduardo Bolsonaro’s overtures to Donald Trump. Its project amounts to something like every man for himself: greater inequality, capitalism without limits, devastation, and supremacism. Will it work? In the United States, just two years into his second term, Trump himself is reaching record levels of unpopularity and may be on the verge of losing Republican control of both the House and Senate in November. Every new beginning is difficult. Whatever the outcome of the second round, the defeats of October 4 show how profoundly the Brazilian left will have to rethink and rebuild. But just as it would be foolish to underestimate the seriousness of its mistakes, it would be equally foolish to conclude that rebuilding a political project is no longer possible. History has not ended. The times are moving faster than ever. Originally published in Portuguese by Outras Palavras. English translation by Eric Blanc; I’ve added the subtitles. More We can’t stop the far right at home or abroad without a revitalized labor movement, which is yet another reason why you should become a sustaining supporter of the Emergency Workplace Organizing Committee (EWOC) — one of US labor’s pivotal bright spots. Relatedly, Jacobin published a short piece of mine reflecting on a decade of Bernie Sanders inspiring a whole new generation of young worker organizers.
With Devon Witherspoon deal done, Christian Gonzalez is up next
Betsy Devos, education advocate, business leader, philanthropist
DeVos is a longtime education advocate and one-time U.S. Secretary of Education under President Donald J. Trump.
Philadelphia Reporter Doesn't Believe Eagles' Makai Lemon is Ready
As the Philadelphia Eagles prepare for the first game of the season, the biggest question remains: what will they do to replace AJ Brown's production? I think one thing that people are forgetting is that the Eagles not only have to replace Brown's production with DeVonta Smith, but they also need to replace Smith's production. Smith is going to be the WR1, and rightfully so.
Catalytic confessions and a quest for Matt Damon: PodCAT puts science on mic
PodCAT, hosted by researchers from Rice, the University of Rochester and Penn State University, is a podcast devoted to the science of catalysis, academic careers and the surprisingly personal stories of the researchers themselves.
New policy bans mobile tattoo and piercing businesses
Mobile tattoo and piercing businesses will not be allowed to operate in the north Devon area
We Live In A Cold, Dead Universe, Virtually Devoid Of Life. This Is The Most Optimistic Scenario Available
Take it from someone constantly writing about the Fermi paradox; a cold, dead universe is the best we can hope for.
Devon Witherspoon responds to Christian Gonzalez trumping his historic deal
The wait has finally come to an end for Christian Gonzalez after he was rewarded with his record-breaking new deal by the New England Patriots. Whether the contract stand-off has had any effect on his preparations for Wednesday’s game in Seattle remains to be seen.
Eagles get concerning multi-week DeVonta Smith injury update
This injury update for the Eagles' WR is not good news at all.
Evaluating DeVonta Smith as WR1
Though he has been a number one receiver before in his career, this past Sunday was DeVonta Smith's debut as the top receiver on the depth chart in the
A look under the hood at the Devon Witherspoon extension
The Pro Bowl cornerback is set to torment quarterbacks into the next decade after signing an extension
Motorola's 2027 flagships will officially support GrapheneOS
This is the de-Googled, more secure version of the Android Open Source Project. GrapheneOS, the modified version of Android that is devoid of Google while...
I've Always Bought AirPods Pro, But AirPods 5 Might Be My New Pick
BGR's own Connor Jewiss has long been a devotee of Apple's AirPods Pro, but some changes made to the new AirPods 5 base model might sway his next purchase.
Devon Witherspoon congratulated by teammates on Hard Knocks
ICYMI: Devon Witherspoon being congratulated by his teammates is must-see wholesome content.
Sony's PlayStation disc plant is losing 10 percent of its volume in 2028, not 90
Sony’s PlayStation disc plant is losing 10 percent of its volume in 2028, not 90 Sony won’t license disc pressing to anyone else, Microsoft does, and a former PlayStation boss thinks that’s the whole problem. When Sony DADC chief Dietmar Tanzer spoke with an Austrian broadcaster in July about PlayStation disc production at the Thalgau plant, a number of press outlets misunderstood the report, writing that production would fall to a tenth of current levels. It won’t. Sony DADC confirmed to Game this week that the figure is a 10 percent decline, not a decline to 10 percent. “To clarify and avoid any misleading information: in that statement Dietmar anticipated an overall product volume decline by 10 percent, not a decline down to 10 percent,” a spokesperson with Sony DADC told Game. That figure covers 2028. Tanzer didn’t put a number on the years after, and the spokesperson declined to comment further. What we do know is that on July 1, PlayStation announced that physical game disc production for all new games releasing on PlayStation consoles will be discontinued starting January 2028 and that the transition has no impact on games that have already released in disc format or will be releasing in disc format prior to that month. “So, there will be reorders going to the market after January 2028,” the Sony DADC spokesperson said. “For details around that I would ask you to liaise with the PR team from PlayStation, as we can’t speak or comment on their behalf.” PlayStation officials did not respond to questions about reorders or other disc-related matters. But I did recently speak with Shawn Layden, Game Industry Strategic Advisor and former chairman of SIE Worldwide Studios, who called a future without physical PlayStation discs “depressing, but solvable.” then added, “I think.” The chief hurdle to third-party manufacturing of collector’s editions or any other version of a PlayStation game disc is that Sony owns the proprietary process to press those discs, Layden said. “And unless they decide or determine a way to license that to some of these bespoke disc manufacturers, there’s no way to make it happen,” he said. Layden was careful to add that he understands the concept but doesn’t have “line of sight on the particulars.” “Depressing but solvable, I think.” — Shawn Layden Microsoft already licenses replication to outside plants. Xbox discs are pressed by manufacturers Microsoft certifies as Authorized Replicators, a term defined in its publisher agreements, with the approved list set at the company’s sole discretion and Microsoft retaining the right to halt manufacture. The structure is still in place today: publishers select an Authorized Replicator in Partner Center and submit a bill of materials created with a Microsoft representative. Sony, by contrast, presses PlayStation discs through Sony DADC, its own manufacturing subsidiary. No one I spoke with said they were in discussions with Sony about doing that, and PlayStation hasn’t responded to questions about whether it would be open to a licensing deal. There is an obvious reason Sony might not want to. Niko Partners analyst Daniel Ahmad pointed it out on the day of the announcement: it’s a platform-led decision, he wrote, designed to cut costs, eliminate the resale market, and drive all revenue through the PlayStation Store. The math is not subtle. On a $70 third-party game sold through the PlayStation Store, Sony keeps $21. Sold at retail, Ahmad says, it earns about half that. Licensing disc replication to an outside manufacturer might not be worth it. And even if it were, it seems unlikely that such a deal would come from boutique companies like iam8bit, which sells collector’s editions of video games. “We would absolutely love to find a way forward to continue making physical PlayStation games,” said Jon Gibson, co-owner and co-creative director of the company. “We are big believers in giving humans the option to truly own media. If we can play a role in helping make that a reality for the future of PlayStation games, count iam8bit in!” If it were to happen, it would most likely be with a company like Conectiv Supply Chain Solutions, a Memphis-based manufacturer of optical discs and vinyl records that also runs third-party logistics, fulfillment and distribution for packaged media. The company, which was formed in 2025 when Los Angeles private equity firm Variant Equity Advisors purchased Vantiva’s Supply Chain Solutions division, traces its lineage back to Technicolor. When it sold the division, Vantiva described the business as having served video game creators for more than 25 years. Conectiv is also buying, not shrinking. Last month it acquired SDS, the distributor for Universal and Warner Bros. home entertainment, consolidating those studios’ packaged-media pipeline from pressing plant to retail shelf. I reached out to Conectiv and its CEO, but haven’t heard back. Layden pointed to music and books in our discussion about the ongoing value of physical media. “No one ever saw the comeback of cassette tape,” he said. “And vinyl didn’t so much come back. The flame went down, the fire’s dying, but the ember was always there, and it just kind of came back. Much like the book business. We thought we’d all be on Kindles right now. “I believe that physical media is crucial and important. One of the things that makes us gamers, one of the core game mechanics, going back to the beginning of time, is collecting stuff. “Did you get all the diamonds in Crash Bandicoot? Did you get all the stars in Mario? And we like to collect our games. And we have a game shelf. And we put all our boxes up there. And if you’re super hardcore, when you buy a game, you buy two copies, right? One stays in the shrink wrap, and you play the other one. What happens to that important cultural part of the gaming world? You know, we buy the steelbook and the three-disc Final Fantasy set and the figurine and, you know, you can’t download any of that. “What happens to that?” And Layden believes it shouldn’t have been a revenue question for PlayStation. “This was a core thing to the experience of our most devoted fans,” he said. “Yeah, it’s fan service. Why would we take that away? Well, we can’t afford to. It’s already 120 bucks, you know, limited edition special purchase onyx box version of whatever, and those sell at a higher rate than the box selling at $69.99 does. So yeah, the market has said they will continue to buy them. You’re just saying you just don’t want to make them anymore.” Layden said he was recently talking with someone about these sorts of business decisions and how they’re made. Too often, he said, it’s all about the financials and nothing else. “OK, we can do this and save this much money, or we can invest this to look at that outcome, or we can do this and have this happen over there, or move this team to Sri Lanka,” he said. “But each one of those, someone also has to have a ledger there saying, ‘OK, what is the brand impact from that move?’ “Iif you can’t resell it, do you really own it?” — Shawn Layden “If we do that, dollars and cents work out. I get it. That’s just math. But what’s the brand impact? Are people going to say, ‘Good move, you guys?’ Or are they going to say, ‘We hate you guys. Quit doing that.’ And sometimes they say, ‘We hate you.’ Then you take a note and say, OK, how much of that can we live with? How much ‘we hate you’ is OK. And when does it go over the line? “I see a lot of companies making decisions which, objectively speaking, I don’t know what the dollar end of that was for you, Mr. Company, but your brand value just dropped 30 percent. So I hope it was worth it.” Of course, shifting to a digital-only model for games raises other issues beyond simply wanting to collect. The biggest is ownership. Layden pointed out that once you go to a streaming-only or download-only model, it’s just a digital footprint on a hard drive. “What does ownership mean anymore?” he said. “It’s a genuine question. Well, in fact, it’s not even a question anymore. It’s like you are shifting the model from ownership to accessibility. “And what’s always been true, which people forget, is you’ve never been able to sell your iTunes library. And you can’t sell your PlayStation download library. So if you can’t resell it, do you really own it?” The touching tribute found in the credits for Star Wars Zero Company. Resonance: A Plague Tale Legacy Interview and Hands-On with a Minoan Masterpiece Star Wars Zero Company hands-on: Attack Astromechs, permadeath, and delightfully fatal Rube Goldberg tactics Control Resonant opens up as you get stronger — and as characters start trusting you
DeVonta Smith torches Titans
Philadelphia Eagles WR DeVonta Smith has 10-catch masterpiece against Tennessee
AI Presents Science with a ‘Ship of Theseus’ Problem
Opinion | AI can replace each part of the scientific process, leaving the enterprise recognizable but devoid of human judgment.
22-year-old rides toward future in cattle business
Agri-Ready Profile: Colton Devore is gaining experience the old-fashioned way as a farmhand, learning the skills for his own beef cattle operation.
For World Mental Health Day, a check-up on the music industry
Consider it a musical manifesto devoted to mental health
Eagles Injury Report: DeVonta Smith misses practice, Saquon Barkley limited
The latest news and updates ahead of Week 3.
Sound of Music museum opens where the von Trapp story met Hollywood
SALZBURG, Austria (AP) — An Austrian museum is alive with “The Sound of Music,” a first-ever venue devoted to the classic 1965 singalong movie starring Julie Andrews. The Sound of Music Salzburg museum, situated in an Austrian city famed for music and perhaps best known as the home of Wolfgang Amadeus Mozart, opened Sunday. The
Loudoun County's Posh Porch Company creates stylish fall displays
Growing up in South Riding, Devon Szklennik always appreciated how her mom, Greta Davies, would transform their home with decorations each holiday season.
‘My Guardian and Protector’: Natalie Harp letters express her devotion to Trump
President Donald Trump’s close aide Natalie Harp expressed her utmost loyalty to him in at least two letters addressed to the president, which were published by The Daily Beast on Thursday amid increased scrutiny of the close aide’s relationship to Trump.
NBC 5 Chicago To Launch A Local Sports & Entertainment Show | Radio & Television Business Report
The NBCUniversal Local property known as "NBC 5 Chicago" is preparing for the September 14 debut of a live, half-hour weeknight program devoted to Windy City sports, entertainment, pop culture, and special guests. Toyota has been brought on as the title sponsor of the offering, which will take the 6:30pm Central time slot.
Florida’s devolving position on science standards
Columnist Pat Beall trains her pen on new Florida school science standards that put evolution and climate change in the back seat.
Zack Baun, DeVonta Smith miss practice for Eagles
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Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Thank you for opening your Chartbook email. Elmer Bischoff, Two Figures at the Seashore, 1957 The only really dynamic job-creator in the US economy is health care: The largest crunch has come in Federal government, which has shed 2.7 m jobs. Source: tchouvkov on Twitter Tech is struggling. [ Joey Politano 🏳️🌈@JosephPolitano The US tech sector continues bleeding jobs in official data released today—overall, employment decreased by 17k last month and is down 69k over the last year That's nearly as bad as the worst of the 2024 tech-cession, and much worse than the 2022 boom or even pre-2020 norms 12:42 PM · Oct 2, 2026 · 15.2K Views 15 Replies · 47 Reposts · 390 Likes ](https://x.com/JosephPolitano/status/2106001807847940232?s=20) The new jobs are all for women. [ Justin Wolfers@JustinWolfers I'm not sure who saw this coming, but so far nearly all the jobs created during the second Trump administration have gone to women. 1:09 PM · Oct 2, 2026 · 33K Views 70 Replies · 146 Reposts · 644 Likes ](https://x.com/JustinWolfers/status/2106008723533533601?s=20) Meanwhile, real wages are being eaten up by modest over-target inflation. [ Heather Long@byHeatherLong The financial pain is real: Wage growth fell to 3% (y/y) in September. That's the lowest in 5 years. Wage growth: 3% Inflation: ~3.4% Inflation has eaten up all wage gains for the average worker since April. Many people are having to make hard choices about what to buy and what … 1:24 PM · Oct 2, 2026 · 37K Views 24 Replies · 275 Reposts · 533 Likes ](https://x.com/byHeatherLong/status/2106012367712620728?s=20) HEY READERS, THANK YOU for opening the Chartbook email. I hope it brightens your day. I enjoy putting out the newsletter, but tbh, what keeps this flow going is the generosity of those readers who clicked the subscription button. If you are persuaded to click, please consider the annual subscription of $60. It is both better value for you and a much better deal for me, as it involves only one credit card charge. Why feed the payments companies if we don’t have to. Subscribe Elmer Bischoff, Bathers, 1960 Americans are disillusioned with higher ed. For contributing subscribers only. Subscribe Where the Chernobyl radiation went. h/t Simon Kuestenmacher aka simongerman600 How Lenin’s love of literature shaped the Russian Revolution - Tariq Ali This, then, was the intellectual atmosphere in which Lenin came of age. His father, a highly cultured conservative, was the chief inspector of schools in his region and much respected as an educationalist. At home, Shakespeare, Goethe and Pushkin, among others, were read aloud on Sunday afternoons. It was impossible for the Ulyanov family – “Lenin” was a pseudonym adopted to outwit the tsarist secret police – to escape high culture. At high school, Lenin fell in love with Latin. His headteacher had high hopes that he might become a philologist and Latin scholar. History willed otherwise, but Lenin’s passion for Latin, and taste for the classics, never left him. He read Virgil, Ovid, Horace and Juvenal in the original, as well as Roman senatorial orations. He devoured Goethe during his two decades in exile, reading and rereading Faust many times. Lenin put his knowledge of the classics to good use in the time leading up to the October revolution of 1917. In April of that year, he broke with Russian social-democratic orthodoxy and, in a set of radical theses, called for a socialist revolution in Russia. A number of his own close comrades denounced him. In a sharp riposte, Lenin quoted Mephistopheles from Goethe’s masterwork: “Theory, my friend, is grey, but green is the eternal tree of life.” Source: The Guardian Elmer Bischoff, The River, 1953 If you’ve scrolled this far, you know you want to click: Subscribe
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