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Faster to Science: A Letter to the Science Community

NASA Science wants to deliver science faster, so we’re changing how we compete and select missions. On Monday, October 26, we will host a virtual NASA Science Town Hall.

Oct 21 • 8:00 PM EDT • Science • science.nasa.gov

A Beloved Hi-Fi Specialist Just Dropped a Gorgeous Pair of Audiophile Loudspeakers

The revered audio brand's entry-level loudspeaker range just got a new addition.

Oct 19 • 2:25 PM EDT • Technology • gearpatrol.com

Freeland Elementary Middle School students enjoy magic show

On Oct. 7, Freeland Elementary Middle School’s fourth-, fifth-, and sixth-grade students, along with their parents, enjoyed an exciting presentation by Joe Romano, titled ‘Is It Magic or Science?’ Through fun…

Oct 17 • 5:55 PM EDT • Science • standardspeaker.com

Headspace Issues Layoffs Following Sword Health Acquisition

It has been a little over two weeks since Sword Health's acquisition of the San Francisco-based digital therapy and psychiatry company Headspace officialy

Oct 16 • 4:21 PM EDT • Health • bhbusiness.com

Headspace Issues Layoffs Following Sword Health Acquisition

It has been a little over two weeks since Sword Health's acquisition of the San Francisco-based digital therapy and psychiatry company Headspace officialy

Oct 16 • 4:21 PM EDT • Business • bhbusiness.com

Joe Romano brings the magic of science to West Hazleton Elementary

On Oct. 6, fourth- and fifth-grade students and their families at West Hazleton Elementary/Middle School enjoyed an engaging and educational presentation by Joe Romano, who combined science and magic to create an unforgettable learning…

Oct 15 • 9:35 PM EDT • Science • standardspeaker.com

Midterm Election Ad Spending Topped $10 Billion, and It’s Still Rising

The campaign is set to be more expensive than the 2024 presidential election cycle, and has already exceeded the ad total booked by the N.F.L. last season.

Oct 14 • 3:08 PM EDT • Politics • nytimes.com

Hazle Township Early Learning Center enjoy science program

On Oct. 5, second-grade students at the Hazle Township Early Learning Center participated in a Title I federally funded parent engagement program, Joe Romano’s Is it Magic or Science? This event was organized to promote literacy within s…

Oct 14 • 12:53 PM EDT • Science • standardspeaker.com

Apple TV 4K Getting A19 Chip and Easier-to-Find Siri Remote

Apple's new Apple TV 4K will be powered by a standard A19 chip, up from the A15 in the current 2022 model, reports Bloomberg's Mark Gurman. Writing in his Power On newsletter, Gurman also said a refreshed Siri Remote will come with a speaker to make it easier to find between couch cushions.

Oct 11 • 11:08 AM EDT • Technology • macrumors.com

Wellcome Global Monitor 2026: Trust in science under pressure

The Wellcome Global Monitor is the world's largest study of how people think and feel about science and health. The 2026 edition draws on surveys of more than 140,000 people in 140 countries, making it a uniquely rich and globally comparable data set on public trust in science.

Oct 10 • 6:36 PM EDT • Science • wellcome.org

Novant Health reduces retirement match amid cost pressures

Novant Health announced changes to its retirement benefits Tuesday that will take effect starting next year.

Oct 7 • 2:41 PM EDT • Health • wect.com

Redmond airport concessionaire ousted after 17 years of business, legal actions taken

Aviano RDM LLC has filed a legal complaint against the city of Redmond after losing both concessions, retail bids for the new airport terminal A national airport hospitality company has […]

Oct 2 • 8:45 PM EDT • Business • redmondspokesman.com

Ashley Tisdale tried to divorce her husband ‘so many times’ after having first baby

Ashley Tisdale opened up about having postpartum depression on her husband Christopher French’s podcast ‘Recovering.’

Sep 30 • 2:40 PM EDT • Entertainment • ew.com

Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL

Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Sep 26 • 9:36 AM EDT • Technology • newsletter.semianalysis.com

JD Sports keeps its nerve on guidance despite a bruising half

JD Sports Fashion PLC (LSE:JD., OTC:JDSPY) has kept its full-year profit forecast intact, even after a rough six months in which earnings slid by a fifth. The FTSE 100 trainers-and-tracksuits giant still expects profit before tax and adjusting items of £700 million to £800 million for the...

Sep 23 • 2:07 AM EDT • Sports • finance.yahoo.com

JD Sports keeps its nerve on guidance despite a bruising half

JD Sports Fashion PLC (LSE:JD., OTC:JDSPY) has kept its full-year profit forecast intact, even after a rough six months in which earnings slid by a fifth. The FTSE 100 trainers-and-tracksuits giant still expects profit before tax and adjusting items of £700 million to £800 million for the...

Sep 23 • 2:07 AM EDT • Sports • ca.finance.yahoo.com

Sword Health is buying Headspace for $300 million, far below its peak value

The all-cash deal values the meditation and mental health app at roughly $300 million, well below the $3 billion valuation it reached at its peak

Sep 16 • 1:03 PM EDT • Health • qz.com

Lil’ Drug Store Products acquires Navajo’s Health, Beauty and Wellness business

Lil’ Drug Store Products, Inc. (LDSP), based in Cedar Rapids, announced the completed acquisition of Navajo Incorporated‘s Health, Beauty, and Wellness business. The acquisition was completed Sept. 4, according to a release. Opened in 1974, the family-owned Lil’ Drug Store Products provides distribution, category management, and brand partnerships across various retail channels such as health […]

Sep 10 • 1:27 PM EDT • Business • corridorbusiness.com

Lil’ Drug Store Products acquires Navajo’s Health, Beauty and Wellness business

Lil’ Drug Store Products, Inc. (LDSP), based in Cedar Rapids, announced the completed acquisition of Navajo Incorporated‘s Health, Beauty, and Wellness business. The acquisition was completed Sept. 4, according to a release. Opened in 1974, the family-owned Lil’ Drug Store Products provides distribution, category management, and brand partnerships across various retail channels such as health […]

Sep 10 • 1:27 PM EDT • Health • corridorbusiness.com

Letter: Rural representation in Deschutes County politics

During the Revolutionary and Civil wars, citizens have fought for freedom. Freedom from tyranny. America has fought throughout the world for people’s rights. “We hold these truths to be self-evident, […]

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Man sentenced after breaking child's fingers while working for health facility

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Roundup: Using AI to better integrate virtual modalities into care delivery

Artificial intelligence enhancements in telehealth aim to bolster care continuity while virtual nursing extends bedside care. Also, Zocdoc integrates with Google Gemini to book appointments while Sword Health is set to acquire Headspace's parent company.

Sep 8 • 2:08 PM EDT • Health • healthcareitnews.com

Healthcare Dealmakers—UHS closes Talkspace acquisition, Sanford's North Memorial deal clears and more

Healthcare mergers and acquisitions are in no short supply as providers, health tech companies, payers and other industry players look to expand their businesses and gain a competitive edge. | Sword Health nears Headspace all-cash acquisition, HCA Healthcare adds dozens of Texas urgent care centers and more healthcare merger and acquisition news from August.

Sep 4 • 8:00 AM EDT • Health • fiercehealthcare.com

Landspout or Dust Devil in Georgetown? Breaking Down the Science

If you were driving around Round Rock and Georgetown Wednesday, you may have had some crazy sights to see. A large swirling vortex was spotted picking up dust a

Sep 3 • 3:29 PM EDT • Science • cbsaustin.com

We Drove the New LS6-Powered 2027 Chevy Corvette Lineup. Here's the One to Get

Whether you choose the 535-hp Stingray, track-ready Grand Sport, or 721-hp Grand Sport X with its electric all-wheel-drive, you'll get the brand-new 6.7-liter LS6 V8 that roars loud and proud.

Sep 3 • 9:00 AM EDT • Technology • thedrive.com

Opinion: If we want to grow Detroit’s philanthropic pie, we have to invite more people to table

Detroit's generosity remains one of our greatest strengths, but some Detroiters have built their lives elsewhere.

Sep 2 • 12:00 PM EDT • Business • crainsdetroit.com

Brad Paisley gets emotional as he sings Dolly Parton duet solo after her death: ‘Never thought it would be about her’

Brad Paisley says his 2005 duet with Dolly Parton, ‘When I Get Where I’m Going,’ has taken on new meaning since her Aug. 25 death at 80.

Aug 30 • 12:17 PM EDT • Entertainment • ew.com

Sword Health and Headspace: A Strategic Deal With Broader Market Implications

This is an exclusive BHB+ article. I did not have Sword Health buying Headspace on my bingo card this year. In fact, if anything I saw both of the digital

Aug 27 • 4:13 PM EDT • Health • bhbusiness.com

Sword Health to acquire Headspace in all-cash deal

Virtual physical therapy platform Sword Health is planning to acquire digital mental health company Headspace in an all-cash deal, according to a regulatory filing from the latter. | The virtual physical therapy and mental health platforms are targeting a September close, per a regulatory filing. A price tag was not disclosed, but is being reported to land between $200 million and $300 million.

Aug 26 • 12:28 PM EDT • Health • fiercehealthcare.com

Sword Health to acquire Headspace, according to filing

Sword Health, a digital health company plans to acquire mental health services provider Headspace, according to a regulatory filing.

Aug 25 • 4:46 PM EDT • Health • statnews.com

Filing Reveals Sword Health’s Plan to Acquire Headspace

Digital health giant Sword Health will continue its expansion into the behavioral health sector with the acquisition of Headspace, effective Sept. 14,

Aug 25 • 1:47 PM EDT • Health • bhbusiness.com

Filing Reveals Sword Health’s Plan to Acquire Headspace

Digital health giant Sword Health will continue its expansion into the behavioral health sector with the acquisition of Headspace, effective Sept. 14,

Aug 25 • 1:47 PM EDT • Business • bhbusiness.com

Next Apple TV Rumored to Have Five New Features, Including Siri AI

According to rumors, the next-generation Apple TV 4K will have at least five new features, including an A17 Pro chip or newer, increased RAM, Siri AI support, an Apple-designed N1 chip with Wi-Fi 7 support, and an updated Siri Remote. Below, we recap everything rumored for the next Apple TV, along with potential launch timing.

Aug 19 • 10:43 AM EDT • Technology • macrumors.com

Three coastal Novant Health hospitals win national heart, stroke care awards

Three coastal North Carolina hospitals have received national recognition from the American Heart Association for their stroke and heart failure care.

Aug 19 • 8:18 AM EDT • Health • wect.com

Corgi races delight fans at Rockingham County Fair

Pounding music blared from loudspeakers at a small enclosure at the Rockingham County Fair on Friday.

Aug 16 • 2:00 PM EDT • Entertainment • dnronline.com

China Box Office: 'Spider-Man: Brand New Day' Retains Crown

Sony's 'Spider-Man: Brand New Day' held onto the top spot at the mainland China box office during the Aug. 7–9 weekend, pulling in $28.9 million.

Aug 10 • 1:44 AM EDT • Entertainment • variety.com

State Police Arrest Wilmington Man Following Multi-Business Burglary Spree - Delaware State Police

The Delaware State Police arrested 53-year-old Eric Jackson, of Wilmington, Delaware, in connection with a series of overnight business burglaries in the greater Wilmington area. On July 21, 2026, at […]

Aug 6 • 2:27 PM EDT • Business • dsp.delaware.gov

Space Science’s Golden Age Problem

The White House released a sweeping vision for the nation's R&D enterprise, with significant implications for space sciences.

Jul 28 • 1:30 PM EDT • Science • payloadspace.com

Skanska delivers $380M LAX project, touts small business partnerships

The contractor said it surpassed all of its targets for inclusion of small, local and veteran-owned business enterprises on the project.

Jul 28 • 5:16 AM EDT • Business • constructiondive.com

Spider Man: Brand New Day First Reactions Praise Tom Holland's Return

Tom Holland is earning rave first reactions for his fourth "Spider-Man" movie, which opens the door to his next era in the Marvel Cinematic Universe.

Jul 28 • 1:35 AM EDT • Entertainment • variety.com

Titans Sign 2-Time Super Bowl Winner Before Training Camp

The Tennessee Titans signed a defensive back a few days before the start of training camp under Robert Saleh The post Titans Sign 2-Time Super Bowl Winner Before Training Camp appeared first on HEAVY.

Jul 25 • 2:22 AM EDT • Sports • sports.yahoo.com

Peptide boom has states scrambling to protect consumers, Post investigation finds

The Post surveyed states’ pharmacy, medical and nursing boards to reveal the gaping regulatory holes for medspas and peptides.

Jul 24 • 5:00 AM EDT • Health • washingtonpost.com

New Ideas in Science and Research: 50 Years of Air + Space

As the National Air and Space Museum built its collection and its identity, it also needed to find its footing as a place for science and research. In the third episode of our four-part limited series 50 Years of Air + Space, we’re exploring the history of scholarship at the Museum.

Jul 22 • 8:00 PM EDT • Science • airandspace.si.edu

Novant Health cutting some revenue cycle positions system-wide

Novant Health is cutting jobs across its health system, though the number of positions being eliminated has not been disclosed.

Jul 21 • 7:38 PM EDT • Health • wect.com

Tim Murphy, former U.S. congressman and state senator, dies at 73

Former U.S. Rep. Tim Murphy, a Republican from Upper St. Clair, died Sunday. He was 73. Murphy died at his home from an apparent heart attack, according to ColdSpark, the political consultancy that worked on Murphy’s campaigns. A native of Cleveland, Murphy earned a doctorate in psychology from the University

Jul 19 • 2:05 PM EDT • Politics • triblive.com

Students hatch nine chicks for science project at Jones Elementary

Students in Rachel Thacker’s third grade class watched nine chicks hatch.

Jul 14 • 8:26 PM EDT • Science • kbtx.com

UNLV students use science to reduce wildfire risk for Las Vegas wetlands

When Sophia Lorenzana took an ornithology class at UNLV as an undergraduate student, she never imagined it would spark a love for one of the area’s most underrated natural resources: Wetlands Park.

Jul 11 • 10:00 PM EDT • Science • lasvegassun.com

ACCESS Model: behavioral health edition

A new value-based care program for chronic condition management begins July 5. | A new payment model is designed to pay digital health companies based on outcomes in chronic condition management. But where does behavioral health fit? This episode explores that question with SonderMind and Headspace, two companies participating in the model's behavioral health track.

Jul 1 • 9:31 AM EDT • Health • fiercehealthcare.com

The Guardians 2026 Trade Deadline Manifesto

Surveying the landscape a month ahead of the deadline

Jun 30 • 2:52 PM EDT • Sports • sports.yahoo.com

Trafalgar Entertainment Announces Acquisition Of The London Theatre Company

Trafalgar Entertainment is delighted to announce its acquisition of the London Theatre Company (LTC). | The deal includes The Bridge Theatre and a King’s Cross venue which hosts immersive entertainment business, Lightroom.

Jun 30 • 6:53 AM EDT • Entertainment • livedesignonline.com

Heat pump rebate programs spur adoption but threaten small Colorado businesses

A major blindspot around heat pump rebates is just coming into view, and it may change the service industry in Colorado forever.

Jun 22 • 5:30 AM EDT • Business • coloradonewsline.com

New CBA for officials emphasizes competition, creates a "practice squad"

Jun 20 • 10:52 AM EDT • Sports • sports.yahoo.com

UND Athletics, Midco Sports extend broadcast and sponsorship partnership

GRAND FORKS, N.D. -- The University of North Dakota alongside Midco Sports announced on Thursday, June 18 the renewal of their Television and Multimedia Production and Broadcast Agreement, continuing a long-standing partnership that delivers high-quality coverage of UND Athletics to viewers across the country.

Jun 18 • 10:01 AM EDT • Sports • fightinghawks.com

Cardenas enters Chicago mayor’s race with focus on city finances

Cardenas, a former 12th Ward alderman who spent two decades on the City Council and later served as floor leader under former Mayor Lori Lightfoot, announced his candidacy today.

Jun 16 • 1:53 PM EDT • Politics • chicagobusiness.com

Falcons reportedly acquire OT Wanya Morris from Chiefs for 2027 sixth-round draft pick

Jun 11 • 8:18 PM EDT • Sports • sports.yahoo.com

DAZN, DirecTV Latin America strike sports channel deal ahead of World Cup

Sports streaming platform DAZN, backed by British-American billionaire Len Blavatnik, said it had struck a deal to bring DirecTV Latin ​America's DSPORTS channels to its platform in five countries, expanding ‌its soccer offering as the 2026 FIFA World Cup kicks off.

Jun 11 • 7:06 AM EDT • Sports • reuters.com

Bowers & Wilkins’ new 800 Series Diamond D5 is its “most advanced loudspeaker range” yet

The seven-strong line-up includes new finishes and evolved tech.

Jun 4 • 8:15 AM EDT • Technology • whathifi.com

Whitworth University Launches New Bachelor of Science Nursing Program to Strengthen Care and Address Critical Shortages Across the Region

Whitworth University is pleased to announce that its new bachelor of science in nursing (BSN) program has been approved by the Northwest Com...

Jun 3 • 8:00 AM EDT • Science • news.whitworth.edu

Windows' classic 3D Space Cadet pinball is getting a physical re-creation

But there are some real-world constraints that virtual pinball could easily ignore.

May 26 • 12:24 PM EDT • Technology • arstechnica.com

French Open: Sabalenka in first-round action, irked Medvedev battling

World number one Aryna Sabalenka plays Jessica Bouzas Maneiro as several top stars get their French Open campaigns under way on day three at Roland Garros.

May 26 • 6:14 AM EDT • Sports • sports.yahoo.com

Vast Launches Satellite Bus Business Line

The commercial space station company announced this morning that it would start selling satellite buses, specifically targeting the low-cost, high-volume, high-power niche for missions from comms, to EO, to national-security programs.

May 19 • 9:00 AM EDT • Business • payloadspace.com

Developer proposes indoor sports complex on East Brainerd Road

A developer wants to build a large indoor sports complex on East Brainerd Road.Planning documents filed with Hamilton County show a request to rezone property i

May 18 • 2:16 PM EDT • Sports • newschannel9.com

Fifth graders bring history to life at Seminole Science Charter School’s Wax Museum

Families, teachers and classmates walked through the “museum,” stopping at each booth to learn more

May 16 • 2:25 PM EDT • Science • wftv.com

PGA Championship: Bryson DeChambeau, once the toast of golf, is in real trouble now

May 15 • 8:37 PM EDT • Sports • sports.yahoo.com

Where do the 76ers go from here after embarrassing sweep to Knicks?

May 11 • 11:03 AM EDT • Sports • sports.yahoo.com

Aetherflux Rebrands, Pivots Business—and Raises $275M

To better align with its new business, Aetherflux is rebranding to Cowboy Space Corporation.

May 11 • 9:00 AM EDT • Business • payloadspace.com

Day in the life of Headspace CEO Tom Pickett, a former Navy pilot

Headspace CEO Tom Pickett said the first part of his career as a Navy pilot was exhilarating. He still makes time to fly several times a month.

May 10 • 5:43 AM EDT • Business • businessinsider.com

UA Little Rock Professor Joins Board of Institute for Design Science and Public Policy

Dr. Mohsen Rafiei, a faculty member at UA Little Rock, was recently appointed to the Board of Directors of the Institute for Design Science and Public Policy (IDSPP), a nonprofit ... UA Little Rock Professor Joins Board of Institute for Design Science and Public Policy

May 6 • 9:00 AM EDT • Science • ualr.edu

Columbia County sports complex moves forward

A $30 million plan to expand youth sports facilities and draw national tournaments to land near the new hospital moved forward this week.

May 5 • 10:58 PM EDT • Sports • wrdw.com

Richwoods students dance the prom night away at Venue Chisca

Richwoods High School students and their dates enjoyed prom night Saturday at Venue Chisca in Peoria's Warehouse District.

May 3 • 5:00 AM EDT • Entertainment • pjstar.com

Marta Kostyuk celebrates biggest title of career with back handspring

Kostyuk defeated Mirra Andreeva to win the Madrid Open and capture her first WTA 1000 title of her career

May 3 • 4:19 AM EDT • Sports • sports.yahoo.com

Researchers Discover Critical GitHub CVE-2026-3854 RCE Flaw Exploitable via Single Git Push

CVE-2026-3854 (CVSS 8.7) enabled GitHub RCE via git push, risking cross-tenant access to millions of repositories.

Apr 28 • 2:19 PM EDT • Technology • thehackernews.com

Walmart Simplifies Streaming Ads for Mid-Sized Business

Walmart Connect has added two new resources for connected TV (CTV) advertisers: a curated marketplace within Walmart DSP called Connect Select and an

Apr 27 • 12:19 PM EDT • Business • pymnts.com

New lakeside bar and entertainment stage open at Lakewood Park Campground in Barnesville

A Schuylkill County landmark took another big step forward this weekend by opening a lakeside bar and outdoor entertainment stage and pavilion. Lakewood Park Campground, which is located in the Barnesville section of Ryan Township, opened…

Apr 25 • 6:00 PM EDT • Entertainment • standardspeaker.com

U.S. Forging a Healthier Oceania Through Trump Administration's America First Global Health Strategy Through Bilateral Health Memorandum of Understanding with Papua New Guinea - U.S. Embassy & Consulates in China

United States Forging a Healthier Oceania Through Trump Administration’s America First Global Health Strategy Through Bilateral Health Memorandum of Understanding with Papua New Guinea Press Statement Thomas “Tommy” Pigott, Principal Deputy Spokesperson April 23, 2026 Yesterday the United States and Papua New Guinea signed a five-year bilateral Memorandum of Understanding (MOU) through the Trump Administration’s America First Global Health Strategy. The landmark health MOU focuses on effectively addressing emerging infectious diseases and ongoing outbreaks, building and maintaining surge-response capacities, and enabling Papua New Guinea’s government to independently manage new health threats before they spread internationally. Working with Congress, the United States intends to provide $15 million through December 2030 through the jointly decided health MOU, building on decades of progress in reducing HIV infections and transmissions in Papua New Guinea. The government of Papua New Guinea intends to allocate up to $3 million to disease control programs and strengthen health systems at the national and provincial levels. Up to $5 million under the health MOU will directly support global health security funding, advancing our shared commitment to health security in the region. Through the signing of this $18 million MOU, we are bolstering infectious disease prevention and response by leveraging cost-effective, nationally-driven approaches, with the goal of increasing Papua New Guinea’s health system self-sufficiency. America First Global Health Strategy Memoranda of Understanding (MOUs) signed so far represent more than $20.6 billion in new health funding, including more than $12.8 billion in U.S. assistance alongside $7.8 billion in co-investment from recipient countries, building on decades of progress fighting HIV/AIDS, malaria, tuberculosis, and other infectious diseases around the world. As of April 22, the State Department has signed 32 bilateral global health MOUs with Angola, Bolivia, Botswana, Burkina Faso, Burundi, Cambodia, Cameroon, Côte d’Ivoire, the Democratic Republic of the Congo, the Dominican Republic, El Salvador, Eswatini, Ethiopia, Guatemala, Guinea, Honduras, Kenya, Lesotho, Liberia, Madagascar, Malawi, Mozambique, Niger, Nigeria, Panama, Papua New Guinea, the Philippines, Rwanda, Senegal, Sierra Leone, Tajikistan, and Uganda.

Apr 23 • 10:36 PM EDT • Health • china.usembassy-china.org.cn

Eugene Civic Alliance, Kidsports complete $48M campaign for Civic Park sports complex

A years-long effort to turn the former Civic Stadium site into a community sports complex has reached a major milestone in Eugene, with organizers announcing th

Apr 23 • 6:26 PM EDT • Sports • kval.com

Toronto 'Godspell' Doc 'You Had To Be There' Acquired By Greenwich Ent.

The 1972 'Godspell' doc 'You Had To Be There,' about the show that launched Gilda Radner, Martin Short and more has been acquired by Greenwich Ent.

Apr 23 • 12:00 PM EDT • Entertainment • deadline.com

NFL makes its case to FCC

Apr 22 • 9:43 AM EDT • Sports • sports.yahoo.com

Broadening the Trump Administration’s America First Global Health Engagement In South and Central Asia - United States Department of State

On April 6, the United States signed a bilateral health cooperation Memorandum of Understanding (MOU) with the Republic of Tajikistan under the Trump Administration’s America First Global Health Strategy (AFGHS). This breakthrough MOU marks the first bilateral health cooperation signed in the South and Central Asia region and aims to protect Americans from infectious disease threats while strengthening U.S.-Tajikistan relations. Through the MOU worth $78 million and working with Congress, the […]

Apr 7 • 6:17 PM EDT • Health • state.gov

Advocates Ready For NASA Science Funding Fight, Part II

Once again, the Trump administration has proposed an $18.8B NASA budget that would make large cuts to science and STEM missions. And—once again—advocates and lawmakers are saying they won’t stand idly by while programs are gutted.

Apr 7 • 1:30 PM EDT • Science • payloadspace.com

Charting a New Phase of Trump Administration's America First Global Health Strategy in Asia, Beginning with Cambodia - United States Department of State

On April 2, the United States signed a bilateral health cooperation Memorandum of Understanding (MOU) with the Royal Government of Cambodia through the Trump Administration’s America First Global Health Strategy (AFGHS). This landmark five-year MOU is the first to be signed through the Trump Administration’s AFGHS in Asia, and advances shared global health goals, such […]

Apr 6 • 8:48 PM EDT • Health • state.gov

Stop pasting this into AI — 7 things you should never share with a chatbot

AI tools aren’t designed to store sensitive information like private documents or bank details — so don’t treat them like a safe

Apr 6 • 1:30 AM EDT • Technology • tomsguide.com

Weatherly Middle School Science Olympiad team qualifies for states

Weatherly Middle School Science Olympiad team has qualified for the state competition at Penn State Altoona on April 25. The team, made up of sixth, seventh, eighth, and ninth grade students, competed at the regional competition at Penn…

Apr 4 • 7:10 PM EDT • Science • standardspeaker.com

State approves 95 new beds for Mission Hospital, denies requests from competitors

A planned expansion at Mission Hospital is raising new questions about competition and healthcare costs in western North Carolina after state health leaders app

Apr 2 • 5:57 PM EDT • Health • wlos.com

Fighting Hawks Sports Partnerships to Launch Uniform Branding RFI on March 31

GRAND FORKS, N.D. – Fighting Hawks Sports Partnerships (FHSP), the sponsorship arm for University of North Dakota Athletics and the Ralph Engelstad Arena, will distribute a Request for Information (RFI) beginning Tuesday, March 31, as it explores potential uniform and apparel branding partnerships across UND Athletics programs.

Mar 31 • 11:01 AM EDT • Sports • fightinghawks.com

Krafton shutters free-to-play PUBG spin-off after two months, in line with policy of using Early Access to "quickly validate a game’s potential"

Company abandons top-down shooter after two months of declining player counts, despite franchise delivering record revenues

Mar 30 • 7:00 AM EDT • Technology • gamesindustry.biz

Medical mover MedSpeed brings on new CFO

Finance and strategy executive Ross Lieb is joining health care logistics company MedSpeed as chief financial officer.

Mar 30 • 6:15 AM EDT • Business • chicagobusiness.com

Quantum computers take a step into real materials science

An IBM quantum computer reproduced experimental signatures of real materials, according to a new preprint from IBM and researcher partners.

Mar 26 • 6:00 AM EDT • Science • research.ibm.com

Implementing the Trump Administration’s America First Global Health Strategy in Angola - United States Department of State

Today, the United States and the Republic of Angola signed a five-year bilateral health cooperation Memorandum of Understanding (MOU), advancing the Trump Administration’s America First Global Health Strategy in Africa. Working with Congress, the Department of State intends to provide $71 million to support HIV, malaria, and global health security programming, while Angola will invest […]

Mar 19 • 12:40 PM EDT • Health • state.gov

Forging Health Partnerships Under the Trump Administration’s America First Global Health Strategy in Honduras and Senegal - United States Department of State

The United States signed bilateral health cooperation Memoranda of Understanding (MOUs) with the Republic of Honduras and the Republic of Senegal, marking significant milestones in advancing the Trump Administration’s America First Global Health Strategy while strengthening our partnerships in the Western Hemisphere and Africa. In Honduras, the Department of State signed a five-year, $46.5 million […]

Mar 13 • 6:41 PM EDT • Health • state.gov

Google Fixes Two Chrome Zero-Days Exploited in the Wild Affecting Skia and V8

Google patches two Chrome zero-days exploited in the wild, urging updates to version 146.0.7680.75/76 to prevent attacks.

Mar 13 • 5:17 AM EDT • Technology • thehackernews.com

Wake County to host measles edition of Ask the Doc Town Hall

Wake County Public Health will hold a special measles-focused Ask the Doc Town Hall on March 10 at 6 p.m., offering residents a chance to learn about symptoms, risks, prevention, and vaccination from local medical experts via Zoom or Facebook Live.

Mar 3 • 7:00 PM EST • Health • wake.gov

Pursuing Sustainable Health Outcomes Under the Trump Administration’s America First Global Health Strategy in the Republic of Guatemala, the Republic of Guinea, and the Republic of El Salvador - United States Department of State

Today, the United States signed bilateral health cooperation Memoranda of Understanding (MOUs) with the Republic of Guatemala, the Republic of Guinea, and the Republic of El Salvador, advancing the Trump Administration’s America First Global Health Strategy across two continents. These MOUs establish frameworks for sustainable, country-led health systems while strengthening disease detection and response capabilities […]

Feb 27 • 8:13 PM EST • Health • state.gov