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PDRN skin care: What the science really says about 2026’s hottest ingredient
For the second article in Cosmetics Business’ ‘Bench to bottle’ series, Rinki Pramanik investigates the science behind PDRN, and if this trending ingredient is just an attractive INCI name, or offers meaningful results
Brewers faithful pack parking lots before NLCS opener
Hours before first pitch, Brewers fans packed tailgates and celebrated the start of the NLCS.
Welcome: Sutter Health Park brings Major League ball to Yolo County
On May 15, 2000, a new attraction opened its gates in the east part of Yolo County.
Can agritourism help small family farms in N.Y. survive?
From pick-your-own apples to hard cider and fall activities, farms are finding new ways to bring customers through the gates. But can agritourism help family farms navigate rising costs and labor challenges?
How Bishop Budde navigates politics in her preaching
So often we become fixated on how our spiritual leaders are navigating political, personal and public matters that we forget we have our own challenges in prayer.
'Staff are scared and exhausted' Concerns raised by Health Department after resident died at Hopkinton assisted living residence
After a resident died in a 99-degree room at the assisted living facility, documents obtained by 5 Investigates show temperatures nearing 90 degrees in several areas of the building.
Mitoma Update: Brighton Confirmed Team News for Sunderland
Fabian Hürzeler navigates a persistent injury crisis as the Seagulls travel north, missing key stars like Kaoru Mitoma while facing a resilient, counter-attacking Sunderland side.
HHS Launches Agency-Wide Actions to Strengthen Vaccine Injury Research, Reporting, and Patient Care
HHS launched a series of actions to strengthen how the federal government identifies, documents, investigates, and responds to health problems.
Q&A: Special Forces vet talks politics and family
Courtesy | Nick Freitas Nick Freitas is an author, political commentator, and social media influencer with more than 2 million Instagram followers. He served in the Virginia House of Delegates as a Republican from 2016–2026 and, before then, was a sergeant and Green Beret in the U.S. Army Special Forces. Freitas gave a lecture on...
JRC science for digital wellbeing
The JRC investigates the implications of digital technologies on people’s health and wellbeing, providing evidence to support EU digital policies. In an era of rapid digital transformation, understanding how technology shapes our well-being is critical.
ANF Investigates: Allegiance Health plans to sell 2 struggling Acadiana hospitals
Allegiance Health Management plans to sell four financially struggling rural hospitals in Louisiana, including two in Acadiana, at the directive of the Louisiana Department of Health. The two Acadiana hospitals involved are Mercy Regional Medical Center in Ville Platte and Acadian Medical Center in Eunice. Both facilities have dealt with a number of problems, including unpaid payroll taxes, broken equipment, overdue bills, the loss of doctors and staff, and a shortage of critical supplies.
ANF Investigates: Allegiance Health plans to sell 2 struggling Acadiana hospitals
Allegiance Health Management plans to sell four financially struggling rural hospitals in Louisiana, including two in Acadiana, at the directive of the Louisiana Department of Health. The two Acadiana hospitals involved are Mercy Regional Medical Center in Ville Platte and Acadian Medical Center in Eunice. Both facilities have dealt with a number of problems, including unpaid payroll taxes, broken equipment, overdue bills, the loss of doctors and staff, and a shortage of critical supplies.
ANF Investigates: Allegiance Health plans to sell 2 struggling Acadiana hospitals
Allegiance Health Management plans to sell four financially struggling rural hospitals in Louisiana, including two in Acadiana, at the directive of the Louisiana Department of Health. The two Acadiana hospitals involved are Mercy Regional Medical Center in Ville Platte and Acadian Medical Center in Eunice. Both facilities have dealt with a number of problems, including unpaid payroll taxes, broken equipment, overdue bills, the loss of doctors and staff, and a shortage of critical supplies.
Say Your Prayers: An Exclusive First Look at Scarlett Johansson in The Exorcist: Martyrs
In Mike Flanagan’s new film, she investigates slayings modeled on the gruesome suffering of saints. But the suspect may be truly inhuman.
Blue Turf Thinkers: Biomedical Research Institute investigates harmful diseases
At each Boise State home football game, the “Blue Turf Thinkers” series honors outstanding groups...
Jagex responds to use of generative AI in RuneScape trailer made by "trusted external partner"
Developer removes promotional material as it investigates situation, says it highlights "an issue with our own processes which we must address"
Aboriginal historian Barry Corr vividly investigates colonisation – but is less convincing on politics
What right did settler society have to intervene in Aboriginal life? The humanitarian tradition has no adequate answers, says Barry Corr.
C.J. Uzomah tailgates with Bengals fans before Jaguars game
C.J. Uzomah tailgated with Bengals fans before the game against the Jaguars on Oct. 4.
Gary Shapiro: why trade shows matter and how to get them right
I ran powerful trade show CES for decades. Bill Gates told me once that trade shows were key for Microsoft. Now, author Robyn Davis is onto something.
From saunas to psychedelics, how a health reporter sorts science from hype
A reporting trip to a sauna conference in Oslo found NPR's Will Stone in a sauna with his clothes and recording gear. In this reporter's notebook, he explains how he investigates the science behind wellness claims.
From saunas to psychedelics, how a health reporter sorts science from hype
A reporting trip to a sauna conference in Oslo found NPR's Will Stone in a sauna with his clothes and recording gear. In this reporter's notebook, he explains how he investigates the science behind wellness claims.
Theaster Gates bets on fine china
The famed, Chicago-based artist's career is taking a new direction with the purchase of Pickard China, the sole remaining maker of fine china in the United States.
WINK News to host Medicare Help Center as 50,000 Lee Health patients face insurance changes
WINK Investigates is hosting a special event to help answer pressing questions from the community.
David Ellison's Skydance is a pretty name. What it stands for isn't
By naming the product of two mergers Skydance, David Ellison relegates two of Hollywood's founding studios to a sub-brand stew and attempts to erase a bunch of controversial hires.
Gates Gains From Business Strength Amid Persisting Headwinds
GTES sees stronger demand, margin gains and data center growth, but weak agriculture and rising costs remain key headwinds.
Troubled Gateshead fail to pay September wages
Gateshead's players and staff do not receive their September wages on time in the same week major funding is withdrawn from the club.
Prosecutors now reviewing case involving two Mobile businesses
FOX10 Investigates has learned the Mobile Police Department has handed over the All Weather Roofing & Construction/ Window Depot USA of Mobile case to the Mobile County District Attorney’s Office.
Pete Davidson slams ‘f---ed up’ criticism of ex Ariana Grande’s body: ‘I don’t like it at all’
The “Saturday Night Live” alum defended his ex as she navigates a lengthy hiatus from public appearances after the release of her “Petal” album.
Surly Gates: Corte Madera’s Tale of Wealth, a Walking Path and Politics
A wealthy Corte Madera private trust claimed Alta Way, a wooded trail, as their own, but neighbors say it belongs to the community.
Immigration hawk warns Trump enforcement ‘missteps’ could come with political price
Mark Krikorian says mixed signals risk frustrating the very voters Republicans need to turn out in the midterms as the administration navigates tensions between its base and business interests.
Vance takes battleground role as Trump opens midterm push
Vice President JD Vance is heading into competitive races this week as President Donald Trump begins his fall campaign push in Oklahoma and Alabama, two reliably Republican states without marquee contests expected to determine control of Congress. The split screen comes as Vance has emerged as one of the administration’s most prominent campaign surrogates and […]
Timken Co. completes sale of belts business to Gates Industrial
Jackson Township-based Timken Co. has completed the sale of its belts manufacturing assets to the Denver-based Gates Industrial Corporation.
Samsung’s Android 17 floodgates are open – updates rolling out for Galaxy S26, S25, more
The floodgates are open. After a delay and staggered starts, Samsung is widely rolling out its Android 17-based One UI...
Pa. Health Department reverses course on new disease-tracking guidance, for now
Pennsylvania’s Department of Health has rescinded a 502-page proposal that could’ve given the agency more control over how it tracks and investigates the spread of diseases — and that spelled out the measures officials can take in response.
Timken Completes Sale of Belts Business to Gates
/PRNewswire/ -- The Timken Company (NYSE: TKR; www.timken.com), a leader in advanced motion technology, today announced the completion of the sale of its belts...
Samsung rolling out Android 17, One UI 9 for more Galaxy S26 users
Samsung is widening the rollout of Android 17 and One UI 9 to the Galaxy S26 series in the US, but the floodgates aren't fully open yet.
PAHO Walk for Health brings together staff, families, partners and delegates ahead of 63rd Directing Council
Washington, D.C., September 27, 2026 (PAHO) — On the eve of the 63rd Pan American Health Organization (PAHO) Directing Council, PAHO staff, families, friends, delegates from Member States, partners and community members came together for the 2026 PAHO Walk for Health, highlighting the importance of physical activity, healthy environments and social connection.
The ‘Beyond the Gates’ Star Who Wrote a Jackson 5 Hit and Preached From a Real Pulpit
Clifton Davis, star of 'Beyond the Gates' and NBC sitcom 'Amen,' wrote the Jackson 5 hit Never Can Say Goodbye and performed it on the soap opera.
Can Science Solve Smoke Taint?
With wildfires an increasing problem worldwide, Chris Boiling investigates the solutions to smoke taint. Read the latest wine news & opinion on wine-searcher
Lewis County investigates ‘confirmed’ case of measles
Lewis County Public Health announced it is “investigating one confirmed case of measles in an unvaccinated resident.”
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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BYU basketball preparing for Jaxon Kohler TRO ruling next week
Kevin Young navigates a volatile legal landscape as the Cougars await a crucial court decision regarding the eligibility of the Michigan State transfer.
Bill Gates warns AI could lead to 'a billion deaths'
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Can Genius Sports (GENI) Justify A Higher Valuation Following Prediction.com Launch?
Genius Sports (GENI) has moved further into the consumer arena with the launch of Prediction.com, a site that aggregates prediction markets and tracks how contract probabilities shift as events unfold. The launch of Prediction.com comes at a challenging time for Genius Sports’ shareholders, with the 30-day share price return down 27.04% and the year-to-date share price return down 46.20%, while the 1-year total shareholder return has declined 54.51%. However, the 3-year total shareholder...
JCPD investigates threatening graffiti at business tied to gubernatorial candidate Hatley
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Netanyahu says attacking Iran was ‘one of the easiest decisions’ he’s ever made
He denounced as “moral cowards” a mass of delegates who walked out of the U.N. General Assembly when he took the podium to speak
Netanyahu says attacking Iran was ‘one of the easiest decisions’ he’s ever made
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Engrams Embedding Entendre: Codesign for Efficient DRAM/SSD Offloading
Engram extends standard token embeddings with learned multi-token lookups. Recurring local patterns retrieve vectors directly, reducing the need to reconstruct them through attention and feed-forward layers. With Engram model architecture optimization, it allows for lower HBM capacity to be needed for models at the same quality. This does not mean there won’t be an insane demand for HBM but it just means that model architecture will continue to innovate around constraints. This model architecture design is naturally codesigned for parameter offloading: each token accesses a few embedding rows whose addresses depend on token IDs, not hidden states. The runtime can prefetch those rows from host DRAM while earlier layers compute, keeping the table outside HBM without transferring entire weight matrices. Our Memory model contains our latest estimates of quarter by quarter HBM, DRAM, & NAND supply and demand. Offloading frees HBM for model weights and KV cache, potentially supporting larger batches or more concurrent sessions. When DRAM becomes the next constraint, NVMe offers another tier. Recommendation systems already cache frequently or recently accessed embedding rows in faster memory while backing colder rows with SSDs. After NVIDIA roadmap had to change due to massively despec’ing Rubin Ultra from 1024GB to now ~200GB of HBM per chip, model architecture optimizations like emgram maybe helpful. Our DeepSeek-V4.1-Flash configuration uses roughly 189 GiB of memory for Engram. We replace it with a memory-mapped (mmap) file and measure serving performance with offload to SSD. Later on in our report, we will show our Engram offloading experiments along with the official InferenceX agentic inference serving results on Engram models like DeepSeekv4.1 Flash across all 6 NVIDIA GPU SKUs along with MI355X. Unsurprisingly, the CUDA Moat is still mogging MI355X on the ultra popular DeepSeekV4.1 Flash model. We also show how even on high capacity HBM SKUs, offloading emgrams to DRAM could result in even better performance for most of the pareto than keeping the emgram in HBM. Our benchmark has been widely reproduced, validated and/or supported by almost every major buyer of compute from Google Cloud to Microsoft Azure to Oracle, to Meta and many more. Furthermore, it has the support of the ML community including from vLLM, LMCache, SGLang, PyTorch, Huggingface and the support of major labs like OpenAI, MiniMax, ZAI, Qwen, Moonshot Kimi, etc. Star the InferenceX GitHub repository if you find the open-source benchmark and data useful!. InferenceX is the only inference benchmark in the world to have TPUv7, Jalapeño, Nvidia Rubin NVL72, AMD, and soon, SambaNova and Trainium. Due to how realistic AgentX scenario is to real world agentic inference workloads, AMD has committed to collaborating on MI455X UALoE72 too. DeepSeek did not release the original paper’s two trained Engram models. We replicated its setup on fineweb-edu using the released code and training hyperparameters, at an estimated 6E18 FLOPs per run. We observed the same U-shape scaling: Engram improved performance over pure MoE baselines. We also reproduced DeepSeek’s results, where earlier-layer representations with Engram resembled those of later layers. Like the original Engram paper, it is possible to probe Engram’s gate scores to see what n-grams DeepSeek-V4.1-Flash makes the most use of. Our gate scan finds names, code fragments, relational phrasing, and boilerplate. These examples prioritize interesting-ness over gate strength. One unexpected result was Wright : Ace Attorney. These examples suggest learned memory optimizes the training objective, not a judgment of which facts deserve storage. Licenses, bibliography fragments, API scaffolding, and website furniture can provide prediction shortcuts, so the value of additional Engram capacity may depend on what survives data preparation. This does not show that table capacity is “wasted”: the evaluation-corpus scan establishes neither training exposure nor the capacity occupied by each category. For offloading, strong gates do not identify cache-hot rows. Low gates do not automatically save reads either: computing the gate requires the retrieved key and undoes the performance gain of a fused kernel. Skipping reads would require a separate usefulness predictor before retrieval. In the original paper’s inference-time ablation, factual-knowledge benchmarks retained just 29–44% of their original performance, while reading comprehension retained 81–93%. This is due to the training–inference mismatch. The resulting degradation therefore measures this trained model’s dependence on Engram, not the performance difference between models trained with and without it. In our ablations, suppressing Engram worsens token likelihood across all evaluated domains, especially encyclopedia text and several code corpora. Surprisingly, GSM8K accuracy stays within measured run-to-run variation and removing Engram has no effect. Engram is not a detachable dictionary beside an unchanged MoE. Removing it changes downstream features and expert selection. We tested whether rerouting hurts or compensates by holding tokens fixed in a teacher-forced experiment on CRUXEval, a code-reasoning benchmark of small Python functions where the model predicts a function’s output from its code and an input, and scoring the reference answer. Removing Engram raised answer loss from 0.2848 to 0.3093 bits/token. Forcing the ablated model to use the original Engram-on expert choices made it worse still, at 0.3375 bits/token. Rerouting partially compensates for the missing memory. Memory features and expert selection work together, rather than following a clean “memory stores facts; experts reason” division. On the same CRUXeval, removing Engram during either phase reduced accuracy and increased generated tokens; removing it throughout produced the largest changes. Keeping Engram for prefill leads to more correct answers than keeping for decode likely due to semantically richer KV cache transferred to decode workers, allowing it to mitigate some of the performance loss. Engram’s table is large, but each lookup is small. DeepSeek-V4.1-Flash requests 24 rows at each of two Engram layers, about 12.4 KiB per processed token position across the model, or 3.1 KiB per GPU when split across four GPUs. Currently as of Day 7 since Model Release, MI355X is still 2-4x worse performance per dollar compared to B200 even when normalized by Mi355X’s lower TCO. Our full total cost of ownership breakdown comes from our AI Cloud TCO Model along with monthly market surveys of over 100+ gpu clouds & gpu cloud customers. On the Day 0 release of DeepSeekv4.1 Flash, NVIDIA vLLM works out of the box with zero issues across all 6 SKUs: H100, H200, B200, B300, GB200, GB300! This was thanks to the amazing work by the NVIDIA & Interact teams! In comparison, AMD vLLM did not work on day 0 for DeepSeekv4.1 Flash.Source: SemiAnalysis InferenceX AMD’s vLLM documentation points to using vllm/vllm-openai-rocm:deepseekv41-flash-0909, but from hour 0 of the model release to hour 23, AMD has not publicly released the image. AMD claims, “SPEED IS THE MOAT,” yet it has still not released it by the 23rd hour. We wish that, going forward, the AMD team has a better process for hour 0 model releases. Eventually when they did publicly release for “day 0” image support, performance-wise, it is currently up to 14.8x worse perf per dollar than H200 and up to 42x worse perf per dollar than B200/B300. The power of the CUDA MOAT is NVIDIA’s collaboration with its massive 6 million-developer community ecosystem including most of the vLLM & SGLang & Tokenspeed maintainers which means that CUDA is optimized on day 0. Overall, AMD did make significant improvements but the performance per dollar is still currently 2-4x worse than B200. AgentX Engram DRAM Offloading Improving Performance The HBM and DRAM offload use the same GPU kernel to select and dequantize rows. With HBM, it reads GPU memory; with Unified Virtual Addressing (UVA), it reads pinned host memory directly. Both support full decode graphs. Moving the table into HBM accelerates only the sparse lookup, leaving decoder computation and communication unchanged, resulting in little overall benefit while consuming memory otherwise available to KV cache. Another benefit of Engram offloaded to DRAM which means you can reduce the communication overhead by using less HBM GPUs per replica. For example, when enabling Engram offloading on B300, we are able to switch from TP4 to now TP2 which improves the pareto curve by up to 1.6x. When iso-model quality, less HBM is required as the engrams could be offloaded to host DRAM. Thus HBM bandwidth matters way more than HBM capacity. For inference workloads where memory bandwidth matters the most, 4-hi HBM provides the best $/bandwidth and therefore lowest cost per token. If China continues to make more and more revolutionary model architecture innovations, soon it could potentially 0Hi HBM stacks. [ ](https://newsletter.semianalysis.com/p/long-live-the-short-king-why-4-hi) [ Long Live the Short King: Why 4-hi HBM Wins ](https://newsletter.semianalysis.com/p/long-live-the-short-king-why-4-hi) Myron Xie, Bryan Shan, and 3 others · Sep 13 [ Read full story ](https://newsletter.semianalysis.com/p/long-live-the-short-king-why-4-hi) Moreover, on B300 and week-0 stack, moving the Engram table back to HBM did not improve results and stay within run-to-run variance. This is a result of the work optimizing DRAM offload, such as async, and overlap. SSD Offloading On B200, we created a unoptimized vLLM fork and stored the Engram tables in memory-mapped files on local SSDs. File backing lets the OS reclaim table pages when other applications need RAM. Pages already cached in memory can be served without reading the SSD again. Furthermore, note that we were unable to turn on GDS The unoptimized SSD implementation changes how rows reach the GPU. It copies row IDs to the CPU, deduplicates them, gathers the requested rows into pinned buffers, copies those rows back to the GPU and dequantizes them. This work runs between segments of the GPU execution graph. Native UVA performs row selection and dequantization directly on the GPU, avoiding the CPU round trip. A warm filesystem cache removes physical SSD reads, but leaves the coordination, row gathering and transfers. This is why a file already cached in RAM can still perform worse than a pinned DRAM table. The comparison measures the whole serving path; it does not separate the time spent on each of these operations. B200 DRAM dominates both measured SSD serving curves in total tokens per dollar and P90 interactivity. Near 125 tokens/s/user, DRAM delivers 121 million total tokens per dollar versus 52 million for SSD. For production serving, SSD offloading is likely not worth the tradeoff. On the B200 configurations we measured, SSD offloading loses on both measures: every observed SSD point has a DRAM alternative that delivers higher P90 interactivity and more total tokens per dollar. The only points where Cheaper storage does not automatically produce a cheaper inference service. Moving Engram to SSD leaves the same four expensive GPUs and the rest of the server in place. Reclaiming RAM only creates an economic benefit if it enables a cheaper server configuration or additional useful capacity. The current unoptimized path provides neither benefit, and the filesystem cache still consumes RAM when table pages are resident. Next we will look at the mechanisms and specific implementation of ngrams from DeepSeekv4.1 Flash, LongCat, Qwen3.8 Flash Next.
Melinda French Gates Shares the State of Women’s Health
Melinda French Gates joins the 3rd Hour of TODAY to talk about new surveys from her organization, Pivotal, which found that one in four women are living in fair or poor health. “Women have been telling us this for years, and yet we’re not making changes to really support them in their health,” she says, adding, "I want to make sure that women can get the care they deserve at the right time in life." Melinda also talks about doubling donations at Olivia Rodrigo’s Daisy Chain Fields Festival and opens up about being a grandmother. "They are just the light of my life," she says of her two grandchildren.
How bad healthcare can derail a woman’s entire life
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Can researchers trust that AI models won’t leak their ideas?
Research funders are asking how they can stop confidential scientific ideas in grant proposals from leaking out through large language models (LLMs), for example if reviewers use AI to help them judge applications. Last week, a row erupted in mathematics after OpenAI announced it had solved a notoriously difficult problem, only for another mathematician to demand answers over whether the company had used ideas he had fed into its models. The spat, and the broader issue of idea leakage through AI models, was discussed by funders at an R&D policy conference held in Paris on September 14. At worst, it threatens to undermine the correct attribution of breakthroughs, one of the foundations of modern science. The mathematics dispute around OpenAI is “certainly something we're looking at” Jason Gallo, head of the newly established Office of Metascience at the US National Science Foundation (NSF), told the Blue Sky Forum, hosted by the Organisation for Economic Co-operation and Development. The controversy started on September 8, when OpenAI announced it had cracked a mathematical problem that had gone unsolved for 90 years. Using a swarm of AI agents, millions of dollars’ worth of computing power and a new internal model, the company said it had finally proved that a long-used formula for modelling fluid dynamics breaks down under certain conditions. However, Tristan Buckmaster, a New York University mathematician who had been independently working with collaborators on the same problem using OpenAI’s Codex tool, hit back with a statement questioning whether the company had snooped on his Codex sessions to gain an advantage. OpenAI has always denied it looked up the “specific user data” of Buckmaster and colleagues. However, the company initially admitted that “while unlikely, we cannot rule out that de-identified data derived from their usage of our products helped improve our models,” although its proofs “differ significantly” from Buckmaster’s. The firm later said that, following an investigation, it concluded that Buckmaster’s Codex prompts “could not have influenced the [OpenAI] system in any way, including through training.”Funder concernYet OpenAI’s initial admission that its model might have ingested Buckmaster’s ideas, then spat them out to its own mathematicians, has scientistsworriedthat their work could leak out if shared with AI. Some AI tools give users an opt-out option to stop their sessions from training the model. If such guarantees can be trusted, this gives scientists some confidence they can use an LLM to develop an idea without the risk of it leaking out.But there’s a bigger potential vulnerability. To win money to investigate ideas, scientists have to share them with funding bodies. These grant proposals are normally kept strictly confidential, to prevent other scientists from scooping them, or to protect commercially valuable intellectual property. To preserve this confidentiality, when the NSF uses AI models, “we have to be sure that it's not making server calls out to an external party, leaking that data,” said Gallo to delegates in Paris. Leaks through reviewersHowever, funders normally use external academic reviewers to assess proposals. And there are growing worries that these reviewers are feeding grant ideas into AI models to help them make a judgement. Research funders have noticed that peer review reports and funding recommendations have “suddenly become much longer, more detailed and complex,” said Diogo Machado, head of the data science unit at Technopolis, a science and technology-focused consultancy. “The sense is that reviewers are increasingly using generative AI in their review work, even where guidelines sometimes forbid it,” he told Science|Business. “This is very difficult for funders to control or prove.” Happening at scaleThis sharing of confidential proposals with AI models is “happening at scale already,” said James Wilson, executive director of the Research on Research Institute, based at University College London, during the debate in Paris. In response, Gallo said the NSF had “strict guidance” around the uploading of proposals to AI models. But he added the NSF was mulling new types of assessment to make sure applicants were truly the originators of their ideas, such as following a short-form proposal with an oral presentation, which would allow the foundation to “really interrogate the investigator on their intellectual contribution.” Related articlesHow can Europe cope with a flood of AI-assisted research grant proposals?The risks and benefits of AI in screening research grant proposals Viewpoint: AI could make scientific overload worse“For us as funders, a lot of the ways to ensure that the application remains the applicant's own intellectual contribution, those ways are quite regressive,” Peter Clifford, head of strategy at Research Ireland, told delegates. “They're maybe ten or 15 or 20 years old, and they don't scale particularly well.” Disputes over the origin of ideas are as old as modern science. Isaac Newton and Gottfried Wilhelm Leibniz spent more than a decade arguing over who invented calculus, for example. And long before LLMs emerged, academics would agonise over how much of their early work to reveal at conferences, in case their colleagues scooped them, Jack Leahy, a senior metascience advisor to the UK government, told delegates. But AI was “accelerating” the “problems of the system,” he said.
Kora and guitar meet in cross-cultural collaboration
BAR HARBOR — Mandingue musician Ballaké Sissoko and British folk artist Piers Faccini share the College of the Atlantic Thomas S. Gates, Jr. Community Center stage in musical conversation and
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Gates Foundation bets $1B on AI to boost global health, agriculture and education
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Wiping out measles impossible due to vaccine hesitancy in rich countries, says Gates
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Iowa candidates turned CyHawk tailgates into campaign stops Saturday, with Republicans and Democrats pitching voters on the issues they say matter most.
Iowa political candidates campaign at tailgates before Cy-Hawk game
Several Iowa political candidates took their campaigns to tailgates Saturday ahead of the Cy-Hawk game in Iowa City.
Iowa, national politicians court voters at CyHawk tailgates
Iowa political candidates for state and congressional offices took to Iowa City Saturday to engage with voters.
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Fact check: Trump, RFK Jr. and others make false claims on night 2 of GOP convention
(CNN) — President Donald Trump delivered another rapid-fire series of false claims on the second night of Republicans’ midterm convention on Thursday. Health Secretary Robert F. Kennedy Jr. did his own barrage of wrongness. And various other speakers uttered statements that were untrue, misleading or missing critical context.Here is a fact check of some of the assertions from the final day of the convention. This is not intended as a comprehensive list of Thursday’s falsehoods.Trump’s many false claimsTrump made numerous false claims, some of which he also made in his longer speech Wednesday.Trump claimed that there were “no empty seats” in the Dallas arena as he spoke Thursday, which was visibly untrue. CNN White House correspondent Alayna Treene, who was there, wrote in a live chat right after Trump made the claim that “I’m looking at rows of empty seats” and that “the idea that there are ‘no empty seats’ is just laughably untrue,” though she also said the room was mostly full. Trump has for years made false claims about supposedly never having had an empty seat.Trump further inflated one of his favorite fictional figures, claiming Thursday that “$22 trillion” in investment has come into the US; on Wednesday, he had put it at “over $20 trillion,” and even that lower figure has no apparent basis in reality. As of the time he spoke Thursday, the White House’s own website claimed there had been “$11.2 trillion” in “major investment announcements” this term, not “over $20 trillion,” and the White House figure was itself a major exaggeration of actual investment.Trump, talking about elections, lied that “there’s never been bigger cheaters” than Democrats; there is no basis for broadly describing Democrats as election cheaters. For the second straight night, Trump falsely claimed that the Biden administration allowed “25 million people” to pour into the country, though that number is nowhere close to correct. Trump again falsely claimed that former President Joe Biden and other Democrats “created the worst inflation in American history,” though even peak Biden-era inflation, 9.1% in June 2022, was far from the all-time record of 23.7%; it was a 40-year high, but the rate then fell sharply before Trump returned to office.Trump also baselessly claimed that Democrats would “defund the police” and give “voting rights and welfare to 25 million illegal aliens” if they won the midterms. Republicans will still control the White House in 2027 and 2028 and the president would be in position to veto any such changes if a Democratic-controlled Congress sought to make them, but there is no indication that Democrats want to do so. Also, even groups favoring strict immigration policies estimate that the total undocumented population is far less than “25 million” or even 20 million.As he did Wednesday, Trump claimed the US now has the world’s lowest prescription drug prices. The assertion is so broad that it is unclear what exactly Trump is referencing. But experts told CNN they highly doubt that the prices for brand-name drugs in the US are generally less than they are in other countries, and the Trump administration has not provided details to prove the claim.“It’s tough to claim that you’re getting the lowest prices anywhere in the world and then also not have any evidence to support that,” said Andrew Mulcahy, a senior health economist at RAND, while Diederik Stadig, senior healthcare economist at financial institution ING, said, “To say that the US now has the lowest drug prices in the world is at this moment not true.”And as he did Wednesday, Trump said “more Americans are working today than ever before” – which is true but nearly meaningless, since the number of people working in the US generally rises over time simply because the population rises over time.“There are more Americans working because there are more Americans. That’s the entire analysis,” Justin Wolfers, a University of Michigan professor of public policy and economics, wrote in his newsletter in August.RFK Jr.’s false claims on the pandemic, Trump’s record and moreFalse claim about Democrats and the 2024 electionKennedy unsuccessfully ran for the 2024 Democratic presidential nomination before withdrawing to run as an independent and then eventually endorsing Republican candidate Donald Trump. In Kennedy’s Thursday convention speech, he complained of how the Democrats handled the nomination race.At one point, he said, “For the first time in history, they cancelled their own convention. No voter ever cast a primary ballot for Kamala Harris, no elected delegate was ever consulted; the party of ‘No Kings’ simply anointed a queen.”Kennedy is entitled to express unhappiness about how quickly Democratic leaders coalesced around then-Vice President Harris after Biden unexpectedly dropped out of the race in July 2024, after the primaries were over and less than four months from Election Day. But it’s not true that the party canceled its convention or that delegates didn’t get any say.The convention was held; it was a four-day event in Chicago in August 2024. Democratic convention delegates officially nominated Harris in a virtual roll call vote in advance of the convention. It’s true that Harris was the only candidate on the roll call ballot, but that’s because she was the only candidate who gathered enough delegate signatures to appear on the ballot.It’s clear that party elites’ backing of Harris played a key role in the unusual nomination process. But Kennedy’s specific allegations that the convention was abandoned and delegates were cut out of the process are not true.False claim that Democrats closed ‘every church’ during the Covid-19 pandemicWhile attacking Democrats, Kennedy claimed that, during the Covid-19 pandemic, “They closed every church in our country for a year.”It’s not true that every church in the country was closed for a year, nor even that every church in a Democratic state was closed for a year.Every state issued some type of guidance or order about social distancing during the Covid-19 pandemic, but many states – including some led by Democrats and some led by Republicans – incorporated religious exemptions into those limitations on social interactions.According to a Pew Research Center analysis from April 2020, 15 states allowed religious gatherings to continue without a limit on their size. That set of states included Colorado, Michigan and Pennsylvania, which all had Democratic governors. And at least two states with Republican governors, Alaska and Idaho, were among the states that prohibited religious gatherings at least briefly.False claim that Trump ‘ended nine wars’Trump has repeatedly claimed that he has ended “eight wars.” Kennedy went one higher on Thursday, declaring, “President Trump has ended nine wars.”That’s false. Trump hasn’t even ended eight wars.Trump’s list of eight includes two situations that were never actually wars during his tenure: a diplomatic dispute between Egypt and Ethiopia and a mysterious supposed situation between Serbia and Kosovo. The list also includes a war, involving Rwanda and the Democratic Republic of Congo, that hasn’t actually ended despite a peace agreement brokered by the Trump administration.In addition, the list includes the war between Israel and Hamas, but Israel continues to conduct frequent attacks in Gaza despite a US-brokered ceasefire agreement. And it includes the brief 2025 conflict between Israel and Iran, though Israel proceeded to join the US in starting another war against Iran in 2026.Claim about reversing a decline in longevityKennedy speaking of the Trump administration, claimed Thursday: “We have now reversed a 30-year decline in longevity. “Kennedy referenced preliminary data that he said he had received from the US Centers for Disease Control and Prevention this week, but it’s unclear what metric of longevity he’s referring to.CDC data shows that US life expectancy had been steadily increasing for decades before a sharp drop during the Covid-19 pandemic. Life expectancy had already started to rebound in 2022, under the Biden administration, and reached a new record high in 2024 before Trump’s second term began.Preliminary data shared by the CDC in July suggests that life expectancy probably hit another record high in 2025.CNN has reached out to HHS for clarification on Kennedy’s comments.Claim that Democrats ‘lost 360,000 children’Speaking about Democrats, Kennedy said: “They somehow lost 360,000 children and they turned our federal government into the biggest child trafficking operation in world history.”Trump and other Republicans have made similar claims. But there’s no basis for the assertion that Democrats “lost” so many children or that the federal government was engaged in human trafficking.A 2024 report from the inspector general for the Department of Homeland Security said Immigration and Customs Enforcement had reported that more than 32,000 unaccompanied migrant children failed to appear as scheduled for immigration court hearings after being released or transferred out of custody between fiscal years 2019 and 2023 – a period that, notably, includes two years and four months under the first Trump administration. The report also said that 291,000 unaccompanied migrant children during this period were not given notices to appear in court.The report said that ICE had “no assurances” these children “are safe from trafficking, exploitation, or forced labor.” But it did not say all the children were actually “lost” and did not definitively assert that any of them were trafficked – let alone that the government was somehow involved in a trafficking operation. And, again, the report spanned parts of both a Republican administration and a Democratic administration.Aaron Reichlin-Melnick, senior fellow at the American Immigration Council, told CNN in 2024: “Long story short, no, there are not 320,000 kids missing. 32,000 kids missed court. That doesn’t mean they’re missing, it means they missed court (either because their sponsor didn’t bring them or they are teenagers who didn’t want to show up). The remaining 291,000 cases mentioned by the (Office of the Inspector General) are cases where ICE hasn’t filed the paperwork to start their immigration court cases.”Vance on inflation, crime and taxes on Social SecurityA false claim about the media and Biden-era inflationVice President JD Vance mocked the media during part of his speech on Thursday. But he made a false claim about Biden-era inflation while lampooning how the media supposedly challenged him over another false claim on that subject.Vance said: “The president and I would go during a campaign, we’d say, ‘You know, inflation is as high as it’s been in 100 years,’ and the fake news would say, ‘No, no, no, it’s as high as it’s been in 68 years.’ That ain’t good, ladies and gentlemen.”Mainstream journalists, at least, wouldn’t say that inflation under Biden was as high as it had been “in 68 years.” Rather, CNN and others noted that peak inflation under the Biden administration, 9.1% in June 2022, was the highest in about 40 years.Vance is entitled to make his general point that this correction still doesn’t make Biden-era inflation sound good, but his specific number was, again, wrong. And he didn’t acknowledge that inflation fell sharply under Biden after hitting the 40-year high, declining to 2.9% in Biden’s last full month in office, December 2024, and 3.0% in January 2025, when Trump and Vance were inaugurated.The rate was 3.4% in July 2026, the most recent month for which data is available.Trump didn’t end taxes on Social SecurityVance claimed, “We’ve ended taxes on Social Security.” Several other convention speakers, including Rep. Lisa McClain of Michigan, Rep. Ryan Mackenzie of Pennsylvania and Ohio House candidate Derek Merrin, similarly said the administration has achieved “no tax on Social Security.”It hasn’t. The big domestic policy bill Trump signed in 2025 did create an additional, temporary $6,000-per-year tax deduction for individuals age 65 and older (which phases out for individuals earning $75,000 per year or more), but as the White House has implicitly acknowledged, millions of Social Security recipients will continue to pay taxes on their benefits even before the temporary new deduction expires after 2028.The Social Security Administration said in 2025 that “the bill ensures that nearly 90% of Social Security beneficiaries will no longer pay federal income taxes on their benefits.Claim about violent crime rate under BidenWhile criticizing the Biden administration, Vice President JD Vance claimed Thursday that the US “became a country where violent crime exploded, unless, of course, you could afford private security.”But violent crime did not explode under Biden. In fact, as FactCheck.org reported last month, data collected and published by the FBI shows that the national violent crime rate was at a lower level in 2023 and 2024, the last two full calendar years of Biden’s term, than it was in 2020, the last full calendar year of Trump’s first term. The year 2020 was highly unusual in many ways – violent crime jumped amid the Covid-19 pandemic – but Biden nonetheless left office with violent crime lower than it was when he took over. In fact, the 2024 violent crime rate was even lower than the 2019 rate under Trump before the pandemic.There was an increase in violent crime during the earlier part of Biden’s term. But given the subsequent decline, it’s misleading at best to claim violent crime “exploded” with no further context.Asked earlier this month about Trump’s similar previous claims to have reversed a Biden-era upswing in violence, crime data expert Jeff Asher said in an email: “No, crime began dropping significantly in 2023 during the Biden administration. Murder fell at record rates in 2023, 2024 and 2025 and, while 2026 may not feature a record decline nationally, it is still on track to see a sizable double-digit decline this year. Violent crime similarly fell nationally in 2023 and 2024, though the drops were more muted than the decline that was recorded by the FBI in 2025.”Other GOP speakersMike Johnson’s false claim about the inflation Republicans inherited from BidenSome other speakers at the convention took aim at inflation under Biden. House Speaker Mike Johnson claimed that “Republicans inherited from the Biden administration record-high inflation.”That’s not true. The inflation rate was 2.9% in Biden’s last full month in office, December 2024, and 3.0% in January 2025, when Trump took over. That’s lower than the most recent rate, 3.4% in July 2026, and nowhere close to the all-time record of 23.7%, which was reached in 1920, or the highest point of Jimmy Carter’s presidency, 14.8%, which was reached in 1980.Johnson correctly said moments later that inflation reached “a 40-year high of 9.1% inflation” under Biden. But a 40-year high is not an all-time record. More importantly, Johnson didn’t explain that 9.1% was much higher than the rate Trump inherited or that the 9.1% rate occurred in June 2022, with roughly two-and-a-half years left in Biden’s term.The cumulative increase in prices from the beginning of the Biden administration to the end was also not the highest in US history. Federal figures show that beginning-to-end inflation under Biden was less than half of that during Carter’s term.What Johnson left out of his claim about a congressional resolutionWhile attacking Democrats as extreme, Johnson said: “Just last week, nearly every Democrat in the House of Representatives voted against condemning socialism and Marxism. They voted against it.”But the resolution didn’t use the word “Marxism.” And Johnson didn’t mention that the resolution wasn’t only about condemning socialism. Rather, it contained other language that Democratic leadership said was the focus of the party’s opposition to the resolution.The resolution’s first provision said it “condemns and denounces socialism in all its forms, including the Democratic Socialists of America, and opposes the implementation of socialist policies in the United States.” But its fifth provision said it “calls for enactment of the SAVE America Act,” Trump’s favored elections bill, which contains various provisions opposed by many Democrats.So while it’s very possible many Democrats would have opposed the resolution even without its expression of support for the SAVE America Act, the call to pass this elections bill served as a poison pill that ensured most Democrats wouldn’t support it.“House Resolution 1490 explicitly calls for enactment of the so-called SAVE America Act, which is the top legislative priority of far-right extremists,” Democratic House leader Hakeem Jeffries said in a statement last week.A New Mexico candidate left out key context in an attack on his opponentGreg Cunningham, a Republican House candidate in New Mexico, used some of his Thursday speech to criticize his Democratic opponent, Rep. Gabe Vasquez. Cunningham said of Vasquez: “He even voted against a resolution honoring the sacrifices and service of the brave men and women in law enforcement who protect, every day, our communities.”But Cunningham left out important context about the resolution. While its focus was expressing support for law enforcement, its preamble contained statements praising the Trump administration and criticizing “leftist activists,” “progressive politicians” and “sanctuary city policies” for allegedly making law enforcement less safe.In other words, a House member might vote against such a resolution, as the vast majority of Democrats did, because they disagreed with conservative components of it, not the general expressions of support for law enforcement. (CNN has reached out to Vasquez’s campaign and House office for comment on his vote.) It’s common for parties to write resolutions in a way that would make it difficult for opponents to support but would open those opponents to campaign attacks if they voted “no.”An Ohio candidate’s misleading attack about Democrats and votingMerrin, the Republican candidate running against Democratic Rep. Marcy Kaptur for a House seat in Ohio, claimed in his speech, “While Democrats talk about letting illegal immigrants vote in our election, Republicans fight for proof of citizenship, photo ID and fair elections.”It’s a big country, so it’s possible some Democrat somewhere is talking about letting undocumented people vote in some election. But Merrin’s claim is misleading at best. There is no proposal from Democrats in Congress to let undocumented people vote in the 2026 midterms – the election Merrin appeared to be referring to when he said “our election” – or vote in future federal elections.CNN has reached out to Merrin’s campaign for an explanation of his claim.House Majority Leader Steve Scalise invoked a similar theme in his speech Wednesday, claiming that Democrats had voted last week “to allow illegals to vote in our federal elections.” But there was no congressional vote on letting undocumented immigrants vote in any elections.Rather, there was a vote on the non-binding Republican resolution that included multiple provisions, including one that “reiterates the notion that American elections are for American citizens only,” one supporting Trump’s favored elections bill and one denouncing socialism.Opposing that multi-clause resolution doesn’t necessarily mean someone supports voting by any non-citizens, let alone non-citizens in the country illegally.This article has been updated with additional items.CNN’s Deja Oliver contributed to this report.The-CNN-Wire™ & © 2026 Cable News Network, Inc., a Warner Bros. Discovery Company. All rights reserved.
David Petraeus: George W. Bush, Political Courage, and the Surge in Iraq
In the wake of the September 11 attacks, President George W. Bush launched what he called the War on Terror. It began with the invasion of Afghanistan in late 2001, which quickly toppled the Taliban and expelled al-Qaeda from its most crucial sanctuary. Then, in early 2003, American forces—with the support of foreign allies like the United Kingdom, Australia, and Poland—attacked Iraq, toppling Saddam Hussein’s regime and installing an occupation force in hopes of quickly transforming the country into a free and democratic state. Instead, the post-regime coalition authority made significant missteps, and a devastating insurgency erupted. And despite President Bush’s 2004 reelection, the war quickly lost popular support among the American public. In early 2007, Bush appointed General David Petraeus, who had already served in Iraq as a two- and three-star general, to lead allied forces in Iraq, which heralded a sea change in American strategy known as “the surge.” As part of our coverage looking back on 9/11 and the world it created, General Petraeus tells the inside story of one of the most consequential moments in the War on Terror. The general’s essay today is both a crucial history and a profile in political courage. It demands reflection as we take stock of the last 25 years. —The Editors By the end of 2006, the war in Iraq was failing. There is no useful purpose in softening that judgment with the passage of time. The bombing of the al-Askari mosque in Samarra by terrorists that February had accelerated sectarian violence and pulled Iraq into an increasingly vicious Sunni-Shia civil war. Al-Qaeda in Iraq and Sunni insurgent groups controlled substantial areas, Shi’ite militias operated with growing impunity in other parts of the country, and the Iraqi security forces were no longer capable of arresting the downward spiral. The strategy of transitioning security responsibilities to Iraqi forces, consolidating American troops on large bases, and progressively reducing the U.S. presence had clearly been invalidated by the escalating violence. The numbers conveyed the horror imperfectly but unmistakably. In December 2006, an average of 53 Iraqi civilians were killed by violence every 24 hours in Baghdad alone. Washington, meanwhile, was approaching its own breaking point. Public support for the war had fallen dramatically, President George W. Bush’s Republican Party had just lost control of both houses of Congress, and the bipartisan Iraq Study Group—of which future defense secretary Robert Gates was a member—had recommended a course that anticipated a substantially reduced American combat role. Many senior military leaders were deeply skeptical of sending substantial additional forces, advocating instead for an accelerated transition to Iraqi forces, the deployment of additional trainers and advisers, or other more modest measures with an eye to withdrawing U.S. forces. Virtually every political incentive pointed toward reducing America’s commitment. President Bush chose instead to increase it, a decision that remains, in my view, one of the most courageous presidential decisions of the 21st century.
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