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Marshall Health Network opens state's first medical respite facility
WCHS ABC 8 provides local news, weather forecasts, traffic updates, notices of events and items of interest in the community, sports and entertainment programming for Charleston and nearby towns and communities in the Tri-State area, including Huntington, Dunbar, Marmet, Montgomery, Nitro, South Charleston, St. Albans, Cedar Grove, Chesapeake, Clendenin, East Bank, Glasgow, Pratt, Cross Lanes, Elkview, Pinch, Sissonville, Big Chimney, Cabin Creek, Chelyan, Davis Creek, Institute, Jefferson, Loudendale, Mink Shoals, Pocatalico, Quick, Quincy, Rand, Buffalo, Eleanor, Hurricane, Nitro, Poca, Winfield, Culloden, Fraziers Bottom, Hometown, Red House, Scott Depot, Teays Valley, Danville, Madison, Hamlin, Logan, Chapmanville, Man, Delbarton, Kermit, Gilbert, Matewan, Williamson, Summersville, Richwood, Flatwoods, Gassaway, Sutton, Spencer, Ravenswood, Ripley, Mason, Point Pleasant, Ashland, Pikeville, Ironton, Portsmouth, Gallipolis, and Athens.
The Wilson Science & Technology Forum at The Jenks Center in Winchester
Walter Hubbard experience with FSD vehicles and Olivia Lanes of IBM speaks about Quantum Computers
Boeing’s Max deliveries fall to lowest count in a year
Boeing delivered just 32 737 Max planes in October, its lowest number of monthly Max handoffs since November 2025. The October delivery rate is significantly lower than it has been
The science behind why ginger ale tastes better on airplanes
Ginger ale tastes crisper and less sweet on airplanes because dry cabin air and lower air pressure at 30,000 feet change how your nose and taste buds work.
Transportation Noise Increases Heart Risk, Even If It Doesn't Disturb Your Sleep
By Dennis Thompson HealthDay ReporterTUESDAY, Nov. 3, 2026 (HealthDay News) — Trains, planes and automobiles all pose a long-term hazard to people’s heart health, a new study says. High levels of transportation noise penetrating a person’s home increase risk of heart attack, stroke and heart ...
Election 2026: City Council races could shift Berkeley's political direction
Voters in four Berkeley City Council districts will decide races where housing, bike lanes and Israel emerged as top issues.
Route 40 Upgrades Finally Reach Finish Line, Despite Business Opposition
City and County leaders celebrated the gains that will come to transit riders and nearby residents as they cut the ribbon on Route 40 upgrades, which include three miles of bus lanes. But the path to get there was a long one.
APEC Business Travel Card Validity Extended
To facilitate business travel within the Asia-Pacific region, China has extended the maximum permitted stay for APEC Business Travel Card (ABTC) holders in China from 60 days to 90 days, effective November 1, 2026. The ABTC provides significant advantages for business travelers from participating Asia-Pacific Economic Cooperation economies. With the ABTC, cardholders can travel freely between member countries without the need to obtain individual business visas for each trip, which greatly reduces the time, cost and administrative burden associated with frequent cross-border travel. Additionally, they benefit from expedited immigration processing, including access to special lanes at airports, although the level of convenience and border clearance infrastructure may differ depending on the country. The card is typically valid for five years, minimizing the need for frequent visa renewals. Furthermore, business travelers are vetted and pre-approved before the card is issued, ensuring smoother entry procedures upon arrival.
Global Health & WASH
The US National Institutes of Health reopened its center and program-project machinery in force. NIGMS is funding Collaborative Program Grants for interdisciplinary teams, NIAID opened both its Immune Tolerance Network and a next-generation R&D call, the NCI runs its Carcinogen Hazard Assessment Monographs program, the National Library of Medicine is funding institutional training in biomedical AI and data science, and NIH reopened its Centers for AIDS Research. The tell: these pay for standing centers and multi-year consortia at institutions with an existing funded research base, not one-off projects, so the fit is an established US research institution, not a single investigator. Disease-specific foundations are again funding the researcher, not just the research. The Parkinson’s Foundation opened its Paul Oreffice Innovations in Care Award and the National Ataxia Foundation its Research Seed Money Grant. The tell, the same one we flagged last cycle, is a named early-career or seed award that builds a pipeline of scientists committed to one condition, so what wins is a researcher willing to specialize. The post-USAID global-health money is routing through a State Department program statement and multilateral innovation funds. The US Department of State’s Bureau of Global Health Security and Diplomacy opened its Advancing Global Health Annual Program Statement, Grand Challenges Canada opened Nexa Lighthouse for climate and health innovation in Asia and the Pacific at USD $250,000 to $2,000,000, and CEPI opened a rolling call on vaccine-manufacturing analytics. The tell: the largest health money this cycle sits in a standing program statement and in staged innovation vehicles, not in a single bilateral grant. Total Estimated Funding Pool: ~$35.4M across discrete grants. (Separately, large national-formula envelopes not counted in this total: U.S. Department of State, Bureau of Global Health Security and Diplomacy (GHSD).) This post is for paid subscribers. This helps support the time and effort it takes to curate and organize these opportunities. Subscribe To keep this accessible to everyone who needs it, we’re happy to offer pay what you can rates. You can find more details here. New opportunities: Paul Oreffice Innovations in Care Award, Parkinson’s Foundation. *New!* *Closing soon!* The Parkinson’s Foundation created the Paul Oreffice Innovations in Care Award to fund clinicians rethinking how people with Parkinson’s disease receive care. The Foundation is using pilot funding to move promising ideas into testable projects, backing work across four lanes: strengthening community clinician capability, redesigning care models, building patient-centered technologies, and defining the minimum clinical datasets that make better standards possible. It wants hypothesis-driven, clinically grounded projects that can generate evidence strong enough to attract further funding. By opening the door to clinicians at every career stage and strongly preferring projects that involve people with Parkinson’s in their design, the Foundation signals that it values practical, patient-shaped innovation over prestige. The strongest fits are US-licensed clinicians with a focus on Parkinson’s and an institutional home for applied care research. Geographies: united states. Who can apply: Clinicians of all career stages, from fellows to established faculty, who are licensed to care for patients in the United States and have a significant focus on Parkinson’s disease. Physicians must have completed a neurology residency (or justify how their training pathway benefits people with PD); allied health professionals must hold an advanced degree, typically a PhD. Fellows, those in mentored positions, and those within two years of starting an independent position require a mentor and a mentor support letter. The sponsoring institution’s grants office is the authorized recipient and funds are disbursed to the institution. Funding amount: Maximum of $200,000 over two years; up to three awards. Targeted Sectors / SDGs: Health; Innovation; Science & Technology. Deadline: November 1, 2026. Learn more and apply here. Design and Deliver the Next EIT Health Bootcamps, EIT Health. *New!* *Closing soon!* EIT Health is opening its call for consortia to design and deliver the next generation of its health start-up bootcamps, funding the curriculum, masterclasses, mentoring, and investor engagement that turn early health ventures into fundable companies. The organization is using these learning paths to strengthen Europe’s health innovation pipeline across digital health evidence, deep tech and AI commercialization, cross-border investment, and patient access. What EIT Health wants to back is not a single course but durable delivery capacity built by partners who span industry, education, and research. Requiring multi-country consortia and a revenue-sharing stake in the programs signals that EIT Health expects these bootcamps to outlast the grant. The strongest fits are established training providers, universities, and industry partners with proven reach into health entrepreneurs. Geographies: Europe. Who can apply: Consortia only (individuals cannot apply), comprising a minimum of two and a maximum of five independent legal entities. Partners must cover at least two sides of the Knowledge Triangle (industry, education, research), including at least one industry organisation, and at least two entities must be legally established in different Horizon Europe countries. Funding amount: Foundational Learning Path: up to EUR €112,000; Thematic Learning Paths: up to EUR €124,500 per path (up to four thematic projects); up to EUR €610,000 total EIT Health funding available under the call. Targeted Sectors / SDGs: Health; Innovation; Science & Technology; Economic Development & Livelihoods. Deadline: November 2, 2026. Learn more and apply here. Technology Transfer Offices & Entrepreneurship Support Call (Beyond the Lab: From Research to Venture), EIT Health. *New!* *Closing soon!* EIT Health is opening its Technology Transfer Offices and Entrepreneurship Support Call to fund consortia that will deliver the Beyond the Lab: From Research to Venture program for healthcare researchers. EIT Health is using the grant to build local capacity for turning laboratory science into incorporated start-ups, paying experienced technology transfer offices and entrepreneurship support providers to run masterclasses, structured mentoring, and a closing Pitch Day across two cohorts. It wants to back organizations that can walk researchers from discovery to company formation, not just teach theory. Requiring two transfer offices plus one venture-building provider signals that EIT Health values proven commercialization experience alongside academic reach. The strongest fits are European research-commercialization teams with a track record of moving health innovations toward investable ventures. Geographies: Europe. Who can apply: A consortium of two Technology Transfer Offices (representing higher education institutions or research organisations) and one Entrepreneurship Support Provider with demonstrated experience in venture building and start-up support. Applicants may apply for more than one learning path where they can demonstrate the required expertise and capacity for each. Funding amount: Up to EUR €77,000 in 2027 and up to EUR €77,000 in 2028 (up to EUR €154,000 total per consortium over two years). Targeted Sectors / SDGs: Health; Innovation; Science & Technology; Economic Development & Livelihoods. Deadline: November 2, 2026. Learn more and apply here. EIT Health RIS Country Representatives Call (2027-2028), EIT Health. *New!* *Closing soon!* EIT Health is seeking organizations to serve as Country Representatives across eleven Regional Innovation Scheme countries in central and eastern Europe for the 2027 to 2028 period. The money funds a national anchor in each country, an organization that maps the local health innovation ecosystem, connects startups and researchers to EIT Health programs, and builds the stakeholder relationships that let health ventures grow. EIT Health is backing local capacity rather than individual projects, which is why it accepts both single organizations and national consortia that span education, research, and industry. The requirement for co-financing signals that it wants representatives already embedded in their national systems. The strongest fits are established ecosystem builders with deep ties to health innovation stakeholders in one eligible country. Geographies: Croatia; Czech Republic; Estonia; Greece; Hungary; Latvia; Malta; Romania; Serbia; Slovenia; Turkey. Who can apply: Registered legal entities established in one of the eligible EIT RIS countries. Single organisations or national consortia may apply. Consortia must include at least two sides of the Knowledge Triangle (education, research and industry), and all consortium partners must be established in the same eligible country. Suitable applicants have demonstrated experience in healthcare innovation ecosystem development, innovation support and entrepreneurship, start-up acceleration, technology transfer, research and higher education, business support, and stakeholder engagement, with strong links to national innovation stakeholders. Funding amount: Up to EUR €182,000 per Country Representative (maximum funding per project); total call budget up to EUR €1,274,500; EIT Health funds up to 60% of total eligible project costs. Targeted Sectors / SDGs: Health; Innovation; Science & Technology; Economic Development & Livelihoods. Deadline: November 2, 2026. Learn more and apply here. Architects of Trust: Community-Driven Demand Creation for New TB Vaccines, Treatment Action Group (TAG). *New!* *Closing soon!* Treatment Action Group, with funding from Wellcome, is opening its Architects of Trust call to help communities prepare for the new tuberculosis vaccines now moving through late-stage trials. The money backs civil society and community-based organizations to raise awareness, surface local questions and concerns, and press policymakers toward equitable national rollout. By pairing each grantee with an advocacy mentor and running a strategy workshop alongside the Global TB Vaccine Forum, Treatment Action Group is building a durable advocacy bench rather than funding one-off outreach. The two-stage design, starting with a short expression of interest, signals that fit and community rootedness matter more than polished proposals. The strongest fits are locally trusted groups with real TB, immunization, or health advocacy experience and a committed project lead. Geographies: Brazil; Ethiopia; India; Indonesia; Kenya; Malawi; Mozambique; Nigeria; Peru; Philippines; South Africa; Tanzania; Vietnam; Zambia. Who can apply: National, subnational, or regional civil society organizations (CSOs) or community-based organizations based in one of the 14 eligible countries or in Eastern Europe/Central Asia regional networks, with experience in TB, immunization, or other health advocacy and in community engagement or policy advocacy; well integrated into stakeholder networks with membership or affiliation to other CSO or community networks; naming a dedicated project lead (’architect of trust’) who can attend the April 2027 Zaragoza forum in person; and holding (or committing to adopt) organizational policies on safeguarding (bullying, harassment, abuse, and harm), equity, diversity and inclusion, and legal compliance, research practice and governance. Funding amount: Grants of up to US$45,000 will be awarded to 8 CSO partners across 14 high-TB-burden countries plus regional networks in Eastern Europe and Central Asia; each grant funds 12 months of work. Targeted Sectors / SDGs: Health; Governance; Policy & Advocacy. Deadline: November 4, 2026. Learn more and apply here.
Tuesday Thoughts 10/27: Circling the Drain
In which we talk planes, embarrassment, and delaying the inevitable.
Tractor-trailer crash closes part of US-70W Business
Two lanes are closed on US-70W Business after a crash involving a tractor-trailer.
Two longtime rivals seek new audiences in Oregon governor’s race. Who will persuade voters?
Despite the effective rematch from 2022, this year’s campaign trail has pushed both candidates to reach voters in opposing ideological lanes.
Crash blocks all lanes of Highway 501 Business
Officials are asking drivers to avoid the area of Highway 501 Business and French Collins Road in Conway due to a two-vehicle crash
United’s C.E.O. Says It Should Cost More Not to Sit in the Middle Seat
Scott Kirby of United Airlines said that “it’s expensive to fly airplanes” and that airfares may have further to rise.
Ford Racing Parts thrives selling crate engines to gearheads
Collectors replace or upgrade engines in everything from Ford Mustangs, Broncos, F-150s, Fairlanes and Galaxies to Chevy Camaros and Chevelles.
Polaris bowling alley installs central Ohio's second largest screen
Star Lanes Polaris installed an 83-foot-wide, 13-foot-high interactive LED screen that is now the second-largest in Columbus.
Athletic Club left waiting after Rayo Vallecano match abandoned
Rayo Vallecano’s match against Athletic Club was abandoned after supporters repeatedly threw paper planes and small balls onto the pitch during protests against president Raúl Martín Presa. Mundo ...
Rayo Plastic Balls Protest Forces La Liga Match Suspension
Rayo Vallecano’s long-awaited return to their Vallecas stadium ended in chaos on Saturday. The La Liga match against Athletic Club was suspended after local fans repeatedly interrupted play by throwing hundreds of small plastic balls and paper airplanes onto the pitch, a coordinated protest against club president Raúl Martín Presa, in what should have been […] The post Rayo Plastic Balls Protest Forces La Liga Match Suspension appeared first on HEAVY.
US removes all Air Force bombers from Fairford base amid terrorism concerns
The United States has moved long-range bombers back to their American home stations days after the British government arrested a number of individuals in connection with an alleged Iranian plot to target the UK airbase where the planes had been stationed.
9 things I wish flyers would stop doing on planes; ex-flight attendant
I saw far too many people go to the lavatory barefoot or blast music without headphones.
Chris Koza album release concert Oct. 24
Lanesboro Arts is thrilled to celebrate the release of Chris Koza’s latest album, “Millsmoke on the Skyline,” with a concert at the St. Mane Theatre at 7 p.m. on October 24. Chris Koza is a composer and performer based in Denver and Minneapolis. In his writing, Koza both honors and builds on the vast genre of Americana music. For every song that sounds like it could be strummed from a boxcar clacking slowly across a grassy midwestern plain, there’s a tune sailing from a city rooftop, echoing across a valley of streets and traffic, or a melody twisting and shimmering like a dim frequency deep into the starry night.Both as a solo artist and with his band Rogue Valley, Koza has supported and shared the stage with artists such as Brandi Carlile, Gordon Lightfoot, Ingrid Michaelson, The Jayhawks, Neko Case, Kathleen Edwards, Dan Wilson, and many more. His music regularly appears on ABC’s “General Hospital,” “60 Minutes,” and “Good Morning America.” Koza’s song, “Be Wild,” was also featured in a state of Minnesota tourism campaign.#placement_932485_0_i{width:100%;max-width:550px;margin:0 auto;}var rnd = window.rnd || Math.floor(Math.random()*10e6);var pid932485 = window.pid932485 || rnd;var plc932485 = window.plc932485 || 0;var abkw = window.abkw || '';var absrc = 'https://ads.empowerlocal.co/adserve/;ID=181918;size=0x0;setID=932485;type=js;sw='+screen.width+';sh='+screen.height+';spr='+window.devicePixelRatio+';kw='+abkw+';pid='+pid932485+';place='+(plc932485++)+';rnd='+rnd+';click=CLICK_MACRO_PLACEHOLDER';var _absrc = absrc.split("type=js"); absrc = _absrc[0] + 'type=js;referrer=' + encodeURIComponent(document.location.href) + _absrc[1];document.write('');Koza’s latest offering, “Millsmoke on the Skyline,” grants the newfound outsider perspective of the rich life and golden fleeting days throughout the rural Midwest. Weaving melody and lyrics into vignettes and narratives set in places where love is powerful, dreams are vast, and life is beautiful.The St. Mane Theatre box office will open at 6 p.m. on the day of the concert. Tickets will be sold in person at the door or can be purchased online at lanesboroarts.org. Seating at the St. Mane theatre is first come, first served. Tickets are on sale now for $25 for general admission or $22 for Lanesboro Arts members.The 2026 performing arts season at Lanesboro Arts is made possible by our season sponsor, Poet Refinery, as well as our concert level sponsors, High Court Pub, Krage Insurance Agency & Preble Farmers Mutual, Stone Mill Clothing & Gifts, E2 Boutique/Amish Experience, and The Cottage House Inn, and community sponsors, VIS Plumbing, Granny’s Liquor, Kingsley Mercantile, Batstone CPA, Clara’s Eatery, IGA, Niagara Cave, and Huntington Electric. This event is made possible by the voters of Minnesota through a Minnesota State Arts Board grant, thanks to a legislative appropriation from the Arts and Cultural Heritage Fund. #placement_932489_0_i{width:100%;max-width:550px;margin:0 auto;}var rnd = window.rnd || Math.floor(Math.random()*10e6);var pid932489 = window.pid932489 || rnd;var plc932489 = window.plc932489 || 0;var abkw = window.abkw || '';var absrc = 'https://ads.empowerlocal.co/adserve/;ID=181918;size=0x0;setID=932489;type=js;sw='+screen.width+';sh='+screen.height+';spr='+window.devicePixelRatio+';kw='+abkw+';pid='+pid932489+';place='+(plc932489++)+';rnd='+rnd+';click=CLICK_MACRO_PLACEHOLDER';var _absrc = absrc.split("type=js"); absrc = _absrc[0] + 'type=js;referrer=' + encodeURIComponent(document.location.href) + _absrc[1];document.write('');
NSU STEM Day puts science, technology and more in the hands of area high schoolers
NATCHITOCHES, La. – From flying drones to handling snakes, guiding airplanes, and cracking codes, students from 18 high schools were led through demonstrations, workshops, and guided exploration of all branches
In 'Digger,' Tom Cruise takes a wild swing worth seeing
Tom Cruise has hung off airplanes, performed crazy motorcycle jumps and run around the world for our cinematic entertainment.
Businesses hope new bus-only lanes on East Colfax will boost business after 2-year construction period
A new bus lane opened Sunday on East Colfax from Broadway to Colorado Boulevard, marking the next step in RTD’s East Colfax Bus Rapid Transit project.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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By Nancy Lapid Sept 10 (Reuters) - When hijacked planes brought down the World Trade Center's twin towers on September 11, 2001, roughly 25,000 children were living or attending school nearby in lower Manhattan, and thousands more were in surrounding neighborhoods. Some were infants and ...
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Greenland research institutions halt new US collaborations citing mistrust
Although US President Donald Trump still harbours ambitions to take over Greenland, for US researchers his actions seem to have had the opposite effect. Over the summer, Greenland’s two largest research institutions, the Greenland Institute of Natural Resources and the University of Greenland, both announced policies of not starting new research projects with US researchers.Both institutions cite a mistrust of the US as a motivation for the decision. At the University of Greenland, the change of policy has already led to the rejection of specific proposals for new collaborations, rector Mari Kleist told Science|Business. “The reason is the changed political situation between the US and Kalaallit Nunaat [Greenland], and the uncertainty that the American interest in Kalaallit Nunaat has created,” she said.For the Greenland Institute of Natural Resources, a partially state-funded environmental research institution, the decision was also prompted by a lack of trust in US intentions. In a July interview with local broadcaster KNR, director Josephine Nymand cited concerns about data ownership, US “influence operatives” and social media monitoring of researchers entering the US.The Greenland Institute of Natural Resources has long collaborated with the US National Science Foundation (NSF). The policy change will not affect these existing partnerships but will apply to collaborations with new, “unknown” partners, Nymand said. At the University of Greenland, the policy is the same.The changes come amid proposals of severe cuts to the NSF, which would likely also see the US research presence in Greenland reduced. In spite of this, when asked about the Greenlandic policy change, the NSF remained optimistic of its continued presence in Greenland.“We are grateful to our partners in Greenland for their collaboration in advancing scientific knowledge and training the next generation of researchers. NSF remains committed to the long-term collaborations with Greenland that enable scientific research near communities and on Greenland’s ice sheet,” an NSF spokesperson told Science|Business.Fewer US researchers in GreenlandMost research published on Greenland is on natural science topics such as the cryosphere, ice dynamics, permafrost and climate change. In recent years, US researchers have been the most prolific publishers on Greenland.The US research presence in Greenland goes far beyond the capital of Nuuk, where the two research institutions are located. It includes the Pituffik Space Base in northwest Greenland, various projects in settlements and research stations along the coast, as well as research stations on the Greenland ice sheet itself.The largest of these sites, Summit Station, is located at the highest point of the Greenland ice sheet, about 3,200 metres above sea level, and since the 1980s it has been used for drilling cores out of the ice sheet. These ice cores provide valuable information on the global climate going back at least 100,000 years. About 30 kilometres from Summit Station, the Danish-led Greenland Ice-core Project (Grip), funded by the European Research Council, is also drilling ice cores. Although they initially competed, the relationship between the two research teams has “long been amiable,” Jørgen Peder Steffensen, a Danish researcher who has been part of Grip for more than 40 years, told Science|Business.However, since Trump took office in early 2025, Steffensen has noticed a reduction in US research in the country. “Several of our American partners did not make it into the field this year. Their field seasons were cancelled because they lacked the budget,” he said.He ascribed part of the reduction in US researchers to a renovation of Summit Station. “A very large share of NSF funding has gone into renewing the station. Money has been taken from research and allocated to rebuilding it,” he said.A report published in August by Arctic Hub confirms Steffensen's observations of fewer US researchers. It shows that US research publications on Greenland took a dip towards the end of the period spanning 2015 to 2024. In 2024, before Trump took office, the number of publications had fallen from an average of about 250 articles a year, to just 164, second behind Canada at 169.Data from the NSF logistics provider Battelle also shows a reduction in US research presence in Greenland in recent years. In 2023, Battelle counted 48 projects across 78 locations, but in 2025 that number had fallen to 40 projects across 38 locations. And while relations with US personnel in Greenland have remained strong, some tensions have arisen since Trump took office. “On a personal level, there is nothing. But it’s hanging in the air. It hangs unspoken,” Steffensen said.Cutting ties with US researchers entirely would come at a higher cost for the ice core researchers than the Nuuk-based institutions. To get cargo to and from their bases, both Grip and Summit Station rely on unique, ski-equipped Hercules LC-130 aircraft operated by the New York Air National Guard. Without these, maintaining a research base on the Greenland ice sheet would not be viable on current budgets, Steffensen said. “[If the Hercules planes were not available], we would have to think outside of the box. We would have to use smaller planes, and we would have to build a base closer to the coast. But staying in our current location would be too expensive and it would create a huge carbon footprint,” he said.Suspicious people in NuukIn her explanation of the severed US ties, Greenland Institute of Natural Resources director Josephine Nymand compared the decision to past situations when the institute had to cut ties with China and Russia, the latter due to Russia’s full-scale invasion of Ukraine in 2022. And although the current situation is less severe, the comparison reflects the seriousness with which Nuuk sees the US threats. “From Greenland’s perspective, the US may not look so different from Russia right now: a much larger neighbouring power threatening to invade,” Lin Alexandra Mortensgaard, a researcher of international politics in the Arctic at the Danish Institute for International Studies, told Science|Business. “From a European perspective, it is not a comparable situation, because we are entangled with the US on all possible fronts and do not want to destroy more than is absolutely necessary. But from Greenland’s side, there may well be a need to send a clear signal to the US,” she went on. Suspicions have been fuelled by instances of Trump-affiliated people in Greenland trying to persuade Greenlandic citizens to support a US takeover. The most prolific among them is Tom Dans, a former venture capitalist and pecan farmer who was appointed by Trump as the chair of the United States Arctic Research Commission. Observers fear that he is now using research to achieve a US takeover.“Greenland is a small society with a small population, so when Americans with unclear affiliations wander around, trying to be good friends with people, and you don't know what they want, that creates mistrust. This probably played into the research institutions taking these drastic steps,” Mortensgaard said.Related articles:The US ‘golden age’ science strategy: what Europeans need to knowEU polar research melts into the backgroundAnchor Greenlanders in Arctic climate research, experts tell EU ahead of policy updateAnd although Greenland’s population is small at just 57,000, for Mortensgaard, it serves as a microcosm for the geopolitical situation as a whole: global powers fighting for their interests to the detriment of the common interest. Arctic research already suffered when collaborations with Russia broke down in 2022, she said, so a split with the US would be a serious hit to climate science.“The Arctic climate system does not respect borders or geopolitical divides. When collaboration across those lines suddenly becomes impossible, it is a huge problem for knowledge production,” she said. European alternatives?The Greenland Institute of Natural Resources is funded partly by research grants from external sources like the NSF. To replace the US funding, the institute will have to look for alternative revenue sources, and Nymand said that she is looking to Europe for those. Aside from Denmark, of which Greenland is formally a part, she also noted increased interest in research collaborations from the UK, France and Switzerland. Kleist of the University of Greenland told Science|Business that it was too early to say if the severed US ties would lead to more collaborations with Europe. Meanwhile, Mortensgaard believed that the tensions in Arctic research could well leave room for closer European partnerships, or stronger links with Canada. “I spoke to Canadian researchers who had long-standing relationships with American colleagues and who collaborated with the US Navy, but who had gotten worried that their data on sea ice could be used if Trump suddenly decided to follow through on his threats of invading,” she said. “Like Canada, I think Greenland is considering creating closer ties to Europe and I think European capitals will be open to this,” she said.
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WCHS ABC 8 provides local news, weather forecasts, traffic updates, notices of events and items of interest in the community, sports and entertainment programming for Charleston and nearby towns and communities in the Tri-State area, including Huntington, Dunbar, Marmet, Montgomery, Nitro, South Charleston, St. Albans, Cedar Grove, Chesapeake, Clendenin, East Bank, Glasgow, Pratt, Cross Lanes, Elkview, Pinch, Sissonville, Big Chimney, Cabin Creek, Chelyan, Davis Creek, Institute, Jefferson, Loudendale, Mink Shoals, Pocatalico, Quick, Quincy, Rand, Buffalo, Eleanor, Hurricane, Nitro, Poca, Winfield, Culloden, Fraziers Bottom, Hometown, Red House, Scott Depot, Teays Valley, Danville, Madison, Hamlin, Logan, Chapmanville, Man, Delbarton, Kermit, Gilbert, Matewan, Williamson, Summersville, Richwood, Flatwoods, Gassaway, Sutton, Spencer, Ravenswood, Ripley, Mason, Point Pleasant, Ashland, Pikeville, Ironton, Portsmouth, Gallipolis, and Athens.
Chile declares health alert for hantavirus
The Chile Ministry of Health issued a Health Alert for hantavirus and other diseases, such as some arboviruses and avian influenza. This is the first time this measure has been taken and it will be in effect until July 31, 2027 and it extends from the Atacama region to the Magallanes region. “Hantavirus causes a disease that is endemic to Chile, transmitted by the long-tailed pygmy rice rat that lives in rural and semi-rural areas throughout almost the entire country. As a ministry, we are constantly monitoring its behavior and are very concerned and actively working because this year the virus's lethality has increased, and for this reason, we decided to declare this alert. As of last week, there were 46 confirmed cases and 18 deaths, representing a 39% lethality rate,” reported the Undersecretary of Public Health, Dr. Alejandra Pizarro. Cases have occurred in the regions of Valparaíso, Metropolitan, O'Higgins, Maule, Ñuble, Biobío, La Araucanía, Los Ríos, Los Lagos, and Aysén. By comparison, in 2025, there were 44 infections and eight deaths (18% case fatality rate). The health alert, which is preventative and prepared, will allow for the granting of extraordinary powers in the event of serious health emergencies to strengthen surveillance, ensure timely resource management, hire specialized personnel, implement health control measures, and expedite the acquisition of supplies through direct procurement. The alert does not imply that there is an ongoing epidemic or that the healthcare system is overwhelmed. Subscribe to Outbreak News TV on YouTube “Hantavirus is not exclusively a summer virus, as the long-tailed pygmy rice rat is present year-round. Therefore, we urge everyone to take extreme precautions: avoid touching rodents, ventilate homes before entering if they have been closed, clean unused spaces with water and bleach, and keep garbage covered and food stored away. Furthermore, it is crucial to be aware of the symptoms: fever, intense muscle pain, and difficulty breathing. If someone experiences these symptoms and has been in rural or semi-rural areas where the long-tailed pygmy rice rat may have been present, they should immediately go to a health center and inform the medical staff so that a hantavirus diagnosis can be considered promptly,” the official added. Since December 2025, the Pan American Health Organization (PAHO) has maintained an epidemiological alert due to the rise in hantavirus cases throughout the Southern Cone, and that the Ministry of Health had an epidemiological alert in place since November of last year. Chile eliminates leprosy As mentioned above, the Health Alert decree also covers diseases transmitted by the Aedes aegypti, Aedes vexans, and Anopheles pseudopunctipennis mosquitoes, such as dengue and Zika, which, according to the alert, “have a high epidemic potential, which could generate high demand and overload for health facilities.” For these diseases, the alert is in effect from Arica to Los Ríos. The authority stressed that it is essential to prevent mosquitoes from breeding in stagnant water and to monitor any suspected cases of people arriving from abroad infected with any of these diseases, in order to prevent any of these vectors from biting a sick person and starting to spread the disease. In the case of avian influenza, the alert was extended to the entire country, because unlike other years, the disease has been concentrated in wild and farm birds, not in poultry farms, increasing the risk of exposure for people. Outbreak News Today is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe
Mamdani's commission unveils five ballot proposals on improving government
The questions range from speeding up the construction of bike and bus lanes to establishing a savings target for the city's rainy day fund.
Phone call ban on planes: ex-flight attendants support bill
A new bill would ban phone calls on flights. Former flight attendants say it would be good for passengers and crew.
Learn Science with Dr. V: The science behind the working of an airplane
Magic? Science? Physics? Peer behind the vail at the magical science involved in airplanes.
‘Extremely frustrating:’ Alpharetta businesses fed up with years-long Highway 9 construction project
The project includes widening Highway 9 to four lanes.
Sports without politics is a fantasy and the World Cup proves it
From ancient Greece to Nazi Germany, sport and politics have long been intertwined. Nevertheless, we still imagine that international sport can be kept above the fray and serve as a neutral arena where nations compete on merit alone. In this article, diplomacy scholar Geoffrey Allen Pigman argues the 2026 FIFA World Cup shows this is a dangerous illusion. When international sport is left entirely to revenue-maximizing private bodies like FIFA, it doesn't escape politics, but rather surrenders to its worst expressions. With the 2028 Los Angeles Olympics fast approaching, the IOC must decide whether to learn that lesson or repeat the same mistakes. The largest and most lucrative FIFA World Cup ever draws toward its climactic conclusion amidst a swirl of controversy. Team members, staff, fans, and spectators have been denied their right to enter the United States to participate, and US President Donald Trump intervened with FIFA boss Gianni Infantino to overturn a referee’s call that Trump believed disadvantaged the US national team. It is a moment to step back and reflect on what the purposes of international sport mega-events like the World Cup, and international sport more broadly, are, and what they should be. Does international sport serve public purposes? Is there a public interest? Or is it primarily a private endeavor organized by commercial enterprises to entertain the global public (and generate profit in the process), which is occasionally used by governments and leaders for raisons d’etat? Central to the idea of sport is the principle of fair play, which in the international context demands that games be free from political interference. However, it is impossible to separate sport from politics, all claims to the contrary notwithstanding. The most positive political use of international sport through the millennia has been to facilitate diplomacy. The use of international sport for diplomatic objectives has existed since at least the time of the ancient Olympic Games, around which was instituted the custom of the Ekecheiria, or Olympic Truce, between participating states to facilitate fair competition and diplomatic achievements by ensuring that participants could travel safely to the Olympiad. In his seminal work On Diplomacy (1987), diplomacy scholar James Der Derian characterized the objectives of diplomacy as overcoming alienation and mediating estrangement between governments and between peoples. One increasingly important diplomatic tool in the technology-infused media environment over the past century has been public diplomacy, under which governments and non-state diplomatic actors (e.g. transnational corporations) communicate to global publics about their international policy objectives and to shape their global brand image. Political scientist Michał Kobierecki, in his important book Sports Diplomacy (2020), views sports diplomacy as falling broadly within the ambit of public diplomacy, as international sport intimately involves the participation of global publics as spectators and consumers of global media. Diplomacy scholar Stuart Murray and this author, in a 2013 article, distinguish between international sport used for diplomatic purposes and international sport-as-diplomacy, which encompasses the range of diplomacy that occurs as teams and competitors, spectators and fans, and government officials all converge for international sporting events like the Olympic Games and FIFA World Cup. Diplomacy scholar H.E. Chehabi, in a 2001 article on US-Iran sports diplomacy, describes the interaction between spectators and fans at international sporting events as “people-to-people diplomacy,” in which relationships develop independently of governments and their objectives. Diplomacy by the aforementioned definitions is often unsuccessful. Moreover, all too often the tools of diplomacy may be employed by governments and other actors to thwart or oppose the objectives of diplomacy as characterized by Der Derian. Governments routinely use the tools of public diplomacy to disseminate propaganda, spreading misinformation in the attempt to deceive global publics about their objectives and to create misleading impressions about their brand identity. Within sports diplomacy, the term “sportswashing” has been coined recently to describe how governments invest in and promote international sport to create positive global public impressions of their nations and, in doing so, to distract the global public from their deficient records in areas such as human rights and democratic governance. Murray, in his 2018 book Sports Diplomacy: Origins, Theory and Practice, introduces the concept of sports anti-diplomacy, wherein governments intentionally use international sport to advance aggressive and nationalistic objectives. Obvious historical examples include Hitler’s use of the 1936 Berlin Olympics to glorify his Third Reich and the 1969 El Salvador-Honduras football “war.” SUGGESTED READING The beautiful game made ugly By Emily Ryall FIFA argues that it is and seeks to be apolitical in its stewardship of international Association Football (soccer). FIFA policies governing bids to host the World Cup require uninhibited and non-discriminatory access for players, team staff, and spectators of all participating countries to host nations and venues. It became clear soon after Trump returned to power in the United States in January 2025 that Trump’s political intentions and objectives to limit non-US citizens from living and working in the United States and, in numerous cases, even visiting the country, would collide with FIFA’s host nation policies. Beginning soon after the start of the second Trump administration, US federal authorities imposed restrictions on entry to the United States of citizens of between 20 and 40 countries for any purpose, with only limited exceptions. Federal Immigration and Customs Enforcement (ICE) began arresting non-US citizens in the United States, including persons with and without legal status, holding them in jails, concentration camps, and other detention facilities until they were deported to their home or third countries, where they faced substantive risks to their personal safety. FIFA boss Gianni Infantino, in an effort to ensure the most successful and lucrative World Cup in history, engaged diplomatically with President Trump in an attempt to facilitate entry to the US for World Cup participants. Infantino did all in his power to ingratiate himself with Trump, to the extent of creating a FIFA “Peace Prize,” which he awarded to Trump in December 2025 at a ceremony in the then Trump-controlled John F. Kennedy Center for the Performing Arts in Washington, DC, on the occasion of the World Cup draw. The prize was an ersatz consolation for someone who aspired in vain to win the rather more prestigious and well-known Nobel Peace Prize. And in the run-up to the World Cup, conditions became worse. In February 2026, Trump and Israeli Prime Minister Benjamin Netanyahu launched a war of aggression against Iran, illegal under international law, under the false pretence that Iran’s government was preparing to attack the United States and Israel. During the US aerial bombardment of Iran, US planes bombed Azadi Stadium, the facility where Iran’s national football team trained. As the 2026 FIFA World Cup began, it was clear that Infantino’s efforts had been for naught: the Trump administration would not adhere to FIFA policies governing access to World Cup host nations. World Cup referee Omar Artan, a citizen of Somalia, was denied a US visa to enter the United States to participate in the World Cup. Trump’s government only granted US visas to Iran’s football team ten days before they were scheduled to arrive for the tournament. Numerous members of the support staff for Iran’s team were denied US visas. Iran’s team, which had been scheduled to train in Arizona, was directed to shift its training site to Tijuana, Mexico, notwithstanding that all three of their group stage matches took place at US venues. The US Department of Homeland Security only permitted the Iranian team to enter the US on the day before each scheduled match and then to return to Mexico immediately after playing. Members of Iraq’s and Switzerland’s football teams were delayed for hours by US officials at the US border, and an Iraqi team photographer was refused entry. Spectators and fans from Haïti and Iran were denied entry to the United States altogether. A large number of fans from a range of countries had their applications for US visas rejected. There were multiple off-ramps through which participants could have avoided the negative consequences of Trump’s decisions for the 2026 World Cup. Once it was clear that the Trump government intended to violate the established expectations for World Cup hosts, FIFA could have shifted the matches scheduled to take place in the United States to Mexico and Canada. The three nations were already designated as co-hosts, and host cities and venues had been selected. Once it was clear that FIFA, governed by FIFA boss Gianni Infantino’s dependent and dysfunctional relationship with Trump, would never consider this option on its own, it fell to the national football federations to act. The national federations, particularly some combination of federations of the leading contenders (France, Spain, Brazil, Argentina, Morocco, England, Germany, etc.), could have refused to participate under the US-imposed conditions or, at the least, demanded an ironclad agreement with the Trump government that FIFA policies on access would be respected. ___ International sport is inextricably entangled with diplomacy of different sorts, for good or ill, it cannot be considered to be in the purely private realm and left to revenue-maximizing private actors. ___ Why did neither FIFA nor the national football federations act to protect the interests of players, team staff, referees, fans, and spectators? In essence, the relentless engines of capitalism prevailed over norm observance, ethics, and fair play. The revenue interests of FIFA, sponsors, global media, and host cities won out. FIFA’s managers viewed hosting another World Cup principally in the United States as a veritable pot of gold for FIFA and its collaborators. FIFA has estimated its own revenue over the 2023-26 budget cycle, which includes the 2026 World Cup, at $13 billion, revised up from an initial projection of $11 billion, and 72% higher than the previous revenue cycle. Of that total, FIFA is estimated to have generated $8.9 billion from the Cup itself in revenue from TV rights ($3.92 billion), sponsorships ($2.69 billion), ticket sales ($3.1 billion), licensing rights, and other sources. A joint study by FIFA and the World Trade Organization estimates that the World Cup will contribute over $40 billion to global GDP, including nearly $14 billion in direct visitor spending in the three host countries (but principally in the United States, which hosted the lion’s share of the matches). The FIFA World Cup is now reportedly “the single most lucrative recurring commercial property in global sport.” And yet, notwithstanding the Trump government’s uses of the World Cup for sports anti-diplomacy, and the climate of anxiety that this created for participants and spectators, diplomacy that did not depend upon governments was able to thrive at the World Cup. Examples of successful people-to-people diplomacy were legion, as citizens of towns and cities across the States, as well as in Mexico and Canada, welcomed team members, their families and supporters, to training sites across North America. Fans of different teams joined together in person in stadiums for matches, at watch parties and bars, and at welcome events sponsored by host cities. The joy and camaraderie shared between the citizenry of Boston and Scotland’s “Tartan Army” of fans is but one example of how the “Beautiful Game” brings people together. Friendships forged across continents are likely to endure well beyond the Cup final. Even those achievements cannot be seen as unalloyed, however. As South African football fan Byron Pillay commented to Al Jazeera, “Football is called the Beautiful Game for a reason, for its ability to unite people. But it’s hard to believe in that magic with the politics and war rhetoric off the field of play, especially when one of the tournament hosts is central to that.” Ultimately, the experience of the 2026 FIFA World Cup illustrates that, as international sport is inextricably entangled with diplomacy of different sorts, for good or ill, it cannot be considered to be in the purely private realm and left to revenue-maximizing private actors. As long as there is the possibility of diplomatic progress in mediating estrangement between governments or between peoples, there is a broad and overarching public interest in international sport. Likewise, as it would be difficult to put on an international sport mega-event without international sporting organizations like FIFA and the International Olympic Committee (IOC), global media firms, and companies purchasing sponsorships, public and private interests in international sport must coexist, most likely somewhere on a shifting spectrum between partnership and rivalry or cross purposes. As the World Cup wraps up, the IOC needs to consider its lessons before the scheduled 2028 Los Angeles Olympics if they want to avoid a media-hyped Trump version of the 1936 Berlin Olympiad. The IOC and the National Olympic Committees need to set conditions on and make demands of Trump’s government with clearly articulated consequences for non-compliance, up to and including cancellation of the Games. Time is running out for the IOC, as unlike with the FIFA World Cup, there is no at-the-ready alternate venue for Los Angeles.
Ukraine used balloons, trailers to sneak FPV drones into Russia: FSB
The details echo that of Operation Spiderweb, when dozens of smuggled Ukrainian drones struck high-value warplanes in four Russian airfields.
LA will replace Pico Boulevard parking with bike lanes. Small businesses worry about the impact
Small business owners want a safer Pico Boulevard, but fear losing hundreds of curbside parking spots in the neighborhood.
Trump weighed in on Cabinet squabble over ride for July Fourth flyover
The president encouraged acting attorney general Todd Blanche to fly on one of NASA Administrator Jared Isaacman’s jets despite the FAA’s prior objection to the planes.
UMass Lowell business students help an endangered species: Duckpin bowling
UMass Lowell business students in the Manning School’s Mill City Consulting course helped modernize North Chelmsford Lanes, one of only two remaining duckpin bowling alleys in Massachusetts, while preserving the qualities that have made it …
NASA Webb Uncovers Unusual Galaxy Shaped by Cosmic Collision
Webb uncovers unusual galaxy shaped by cosmic collision: Webb's unprecedented sensitivity across near- and mid-infrared wavelengths cuts through the thick lanes of dust that obscure Centaurus A’s center in visible light, showing a densely packed tapestry of individual stars and an active, everchanging galaxy. These images mark four years of better-than-anticipated performance and successful science operations for the most powerful space telescope in history. Centaurus A is 11 million light-years away from Earth, relatively close in cosmic terms. Yet, unlike most nearby galaxies, it is very active, making it a powerful laboratory for understanding how galaxies and black holes grow and evolve together.
Why are airplanes so cold? It’s for your health.
From combating fainting to helping aircraft work efficiently, planes are chilly for a reason.
Readers Write: Traffic speeds, bike lanes, deportations, political characters, kids these days
On the road, chill out and save money.
Chicago’s Bike Lanes Don’t Hurt Businesses, City Report Finds
As protected bike lanes face opposition in some neighborhoods, city-backed case studies found lanes in a half-dozen corridors have not contributed to a negative impact on economic activity.
Aerial begins in Fort Bend County after mosquito population grows to become public health emergency
Planes will drop pesticides over designated areas around Fort Bend County each evening through Thursday, officials said.
"It's really going to impact us': Troy lane closures worry businesses during peak summer season
Lanes of a major Troy intersection are closing for three weeks — right in the middle of summer. Local businesses say the timing couldn't be worse.
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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Share I’ve recently run several popular posts breaking down data related to sought after legal jobs. General Counsel Big Law Appellate Attorney Here is another in this series. Two Lawyers, One Elite Market Entertainment law can sound like a single professional category. In practice, the lawyers who reach the top of the Hollywood market often look quite different from one another. Consider two attorneys from the 2025 top-entertainment-law universe. Lesley Freeman represents one route: the company-side entertainment lawyer. She is chief legal officer of AGBO, where she oversees company-wide business and legal affairs across film, television, video game and interactive experiences, and technological innovation, after senior legal roles at MGM, Amazon MGM Studios, HBO, and O’Melveny. Daniel Petrocelli represents another route: the outside-counsel trial lawyer. He is chair of O’Melveny’s trial practice and a vice chair of the firm, with a national litigation practice that includes entertainment, sports, and media disputes. Their careers differ by platform, role, practice area, and professional identity. One sits inside an entertainment company; the other practices from a major law firm. One is associated with corporate and governance work; the other with litigation. Yet both fall within the same publicly recognized top tier of Hollywood lawyers. That contrast points to the article’s central question. If there is no single mold for a top entertainment lawyer, are the paths simply idiosyncratic, or do they follow recurring patterns? The data suggest the latter. The attorneys recognized on The Hollywood Reporter and Variety’s 2025 top-attorney lists do not follow one career template, but their paths are not random. They cluster around several defined routes: entertainment-focused private practice, company-side or operator experience, corporate and finance conversion, litigation conversion, public-service-to-litigation pathways, and smaller specialized lanes in labor, employment, and celebrity family law. Across those routes, the recurring ingredients are platform strength, educational capital or Los Angeles market proximity, long career tenure, specialized practice identity, and entertainment-industry fluency. The article examines five dimensions of the top-attorney sample: route into entertainment law, firm or organizational platform, education pipeline, seniority, and practice specialization. Data and Methodology The dataset includes 103 attorneys drawn from The Hollywood Reporter and Variety’s 2025 lists of top entertainment or Hollywood attorneys. For each attorney, the dataset tracks current organization, law school, J.D. year where available, first-known bar admission year, practice area, prior roles, platform type, and route into entertainment law. The sample is best understood as a recognized-attorney dataset, not a census of all entertainment lawyers. It captures lawyers who reached public top-tier recognition in 2025, rather than every lawyer practicing in the entertainment sector. Multiple but Defined Routes Into Entertainment Law The first question is how these lawyers entered the entertainment-law market. Because every attorney in the dataset is entertainment-related by definition, the key distinction is not whether they practice entertainment law. It is how they got there. The largest group followed what might be called the entertainment private-practice route. These attorneys appear to have built their practices around entertainment, media, talent, music, rights, production, intellectual property, or adjacent industry work relatively early. That route accounts for 40 of the 103 attorneys in the sample, or 38.8%.
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