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A Man Was Scrolling Google Maps—Then He Noticed Google Maps Staring Back at Him
The physical forces beneath this eerie floating “eye” in Argentina are even stranger than the shape itself.
Carson College student consultants move regional businesses forward
Regional businesses can receive a semester of consulting support from WSU Vancouver business students, guided by faculty and experienced business leaders, at no cost.
Scientists uncover a hidden map of the brain with 539 distinct regions
Scientists have uncovered a hidden layer of organization in the brain by creating the first detailed 3D map of its lipids, the fatty molecules essential for brain structure and communication. By analyzing millions of measurements from mouse brains, researchers identified 539 distinct chemical zones, revealing patterns and boundaries that traditional brain maps have missed. Surprisingly, even white matter, once thought to be relatively uniform, contains a complex patchwork of chemically distinct regions.
Which games are Fox, CBS broadcasting? NFL Week 5 coverage maps
Which NFL games will be broadcast in your region in Week 5? Here are the coverage maps for Sunday's action.
The midterm maps changed–so could Black political power
New congressional maps in nine states could reshape Black voters’ ability to elect preferred candidates, raising concerns about diluted political influence in s...
After October 7: new faces, changing maps
Al Majalla examines this changed landscape—from Israel's domestic political scene to its external ambitions, where it occupies large swathes of new territory in the West Bank, Lebanon and Syria
See how redistricting will impact MS mental health, drug courts
Redrawn circuit and chancery court maps from 2025 will take effect in January 2027. See how judges say their courts will be impacted.
US Supreme Court orders another look at how Washington state political maps are drawn
Monday’s action will not affect next month’s election. But it could lead to the state’s legislative district boundaries changing before they’re next scheduled to be redrawn in 2031.
SCOTUS order could send WA political maps back to the drawing board
It won't happen before the 2026 midterm elections. But Monday's development is the latest twist in the saga of Washington's redistricting efforts.
US Supreme Court orders another look at how WA political maps are drawn
The U.S. Supreme Court on Monday took action that could set the stage for another redrawing of Washington’s political maps.
Teaching students scientific-storytelling skills to inspire change
The senior capstone course ESCI 191 equips environmental-science majors with digital-storytelling skills to translate complex climate data into compelling narratives to immerse and engage the public.
MedX Health Appoints Monaderm as a Representative for SkinSecure™ Across Europe for Beauty and Aesthetics Research
MISSISSAUGA, Ontario, October 05, 2026--MedX Health Corp. (TSXV: MDX), a data-driven skin health analytics company, today announced the appointment of Monaderm, the Monaco-based skin measurement specialist, as a key European sales agent for SkinSecure™, expanding the commercial reach of its non-invasive, objective biological skin measurement technology, which maps collagen, melanin and hemoglobin non-invasively in living skin in a single 30-second capture, across the European cosmetics and skin
NFL Week 4 TV coverage maps
There are 15 games remaining on the Week 4 NFL schedule. Here is when and where you can watch them.
TV maps for Week 4 of 2026 NFL games
There's a full slate of NFL action Sunday on CBS and FOX. Here's a look at the Week 4 TV coverage maps.
I changed these hidden Google Maps settings; now my Android Auto navigation is miles better
Small tweaks made every drive smoother
The midterm maps changed. So could Black political power
Roughly one in 10 voters will cast ballots in newly configured congressional districts. For Black communities, the changes could determine whether their politic...
Earth Science Week at Museum Features Fossils, Minerals, Maps, and More
Credit: CourtesyCredit: CourtesyCredit: CourtesyCredit: Courtesy SANTA BARBARA, CA—The Santa Barbara Museum of Natural History is celebrating National
Fiery crowd caps Mississippi redistricting hearings. Opponents urge: ‘Leave our maps alone’
Tempers flared Thursday at a packed redistricting hearing at the Mississippi Capitol, where a large majority of speakers criticized what they said was a power grab aimed at diminishing Black political power and further entrenching Republican dominance over state politics.
What's that under construction at Salem's Willamette Town Center?
Crews are preparing to turn a portion of the parking lot at Willamette Town Center into a Maps Credit Union.
Amendment 86 | Redrawing political maps in ‘off cycles’
Colorado voters will decide in November whether to put new constitutional limits on how and when the state’s congressional districts can be redrawn.
Amendment 86 | Redrawing political maps in ‘off cycles’
Colorado voters will decide in November whether to put new constitutional limits on how and when the state’s congressional districts can be redrawn.
The Politics of the Planetary
The French philosopher Guy Debord and Danish painter Asger Jorn built their book Mémoires (1959) out of a collage of purloined material. Newspaper clippings, magazine advertisements, cartoons, cutups of maps…
Bethesda Maps Fallout 76’s Biggest Year Yet, Expanding the Map toward Fallout 3’s Capital Wasteland by Summer 2027
Bethesda has mapped out a truly exciting year of free updates for Fallout 76, including a new map expansion into the Capital Wasteland.
When “DEI” research is cut, what happens to community health?
“I’m just going to run to the grocery store!” How many times have we said this without thinking about it? For most of us, it's usually an easy walk or a short drive to get the cheese we forgot. In reality, though, 13% of the U.S. population (about 39 million people) live in “food deserts,” which means living more than a mile from a grocery store in urban areas and more than 10 miles in rural areas. This was the case for people in Pittsburgh’s Hill District, where a quick run to buy food wasn’t an option. In the 1930s, federal maps marked the Hill as "hazardous" for lending, a practice known as redlining that steered investment away from Black neighborhoods. Decades of disinvestment followed, and residents went about 30 years without a nearby grocery store. This made it hard to keep healthy eating habits and contributed to chronic disease. When a grocery store finally opened in the area in 2013, researchers saw the opportunity and launched the PHRESH study, which initially compared the health of participants from the Hill district to those in the Homewood district. Over time, the study expanded to other factors such as brain health and Alzheimer's risk. Residents like Roderick Blair overcame initial hesitation to share their health data, trusting it would benefit their neighborhood. Then, in August 2026, the NIH abruptly canceled the study’s grant, citing that it was “subjective” and fell outside their scientific scope—an effect of the administration’s interpretation of diversity, equity and inclusion (DEI). Research like PHRESH can help determine what changes in a neighborhood actually improve health, so cutting it has left that question unanswered. Other canceled studies have examined health issues like maternal health, preterm birth rates, or sickle cell disease. Courts have reversed some of these grant cancellations, but not all of them. If we really want America to be healthier, research into why some communities get sicker than others is absolutely critical. The law that created the federal minority health research institute passed with bipartisan support in 2000. But these days, as evidenced by grant cancellations, the political shift in attitudes toward DEI means we often lose access to the health information we need to help all communities thrive. DEI vs. health equity vs. equality and the overlap (or lack thereof) The letters “DEI” evoke very different reactions depending on who you are in the U.S. DEI programs can address gender, disability, age, and other factors, but the fiercest debate centers on race. For some people, hearing DEI brings to mind policies that may have cost them a job or a college seat because they are white. Others see DEI as a matter of justice: a way to expand representation and opportunity for groups that have been historically marginalized. Both perspectives are rooted in lived experience, and both center on the same question: whether hiring and admissions practices are fair. Hiring and admission practices, though related, are not the same as health equity. Health equity is “the attainment of the highest level of health for all people.” It’s the recognition that some groups of people consistently experience worse health outcomes than others. For instance, black mothers die from pregnancy-related complications at three times the rate of white mothers, and rural Americans are more likely to die from issues such as heart disease and cancer. Equity is also often conflated with “equality,” which leads to misunderstanding of how to actually best support communities. Equality ignores the fact that we aren’t all starting life with the same resources or circumstances, whereas equity is about helping people get what they specifically need based on their situation so they have the chance to achieve the same outcome as anyone else. For example, if every household in Pittsburgh got a $30 grocery gift card, that would be equal. But during the decades the Hill District went without a grocery store, that card wouldn’t have helped much. Equity means making sure everyone can actually access a store in the first place. DEI policies can overlap with health equity in many ways. For example, they may help expand access to quality education and stable, well-paying jobs, which in turn can provide health insurance, safer housing, and improved finances—all of which can reduce health disparities. But to make that happen, we first need data to identify disparities in communities and to develop solutions that effectively address them. What we lose when the research stops Community data is important to health equity because: You can’t fix what you don’t see: Data show which communities are most affected by health factors such as infection, heart disease, and cancer. If we don’t know what is happening and where, then we can’t develop interventions to help. Poor health costs everyone: Chronic disease is expensive—both to the individual person and to the overall economy. Understanding what groups of people are most at risk allows us to develop interventions that can save everyone money. Disparities exist for many communities: Health equity includes disparities that exist due to a whole host of factors, such as family background, race and ethnicity, rural vs. suburban residence, gender and sexual orientation, veteran status, disability, and lower income. This means many Americans can benefit from research into differences in health outcomes and how to improve them. Trust is easy to lose: Some participants in the PHRESH study were initially vocal about their concerns about participating. But that trust was earned because the researchers kept their promises and centered their work on the community. When projects are canceled mid-cycle, researchers have no choice but to leave behind communities they had promised to help. This hurts trust in the long run. It’s also a very inefficient use of resources, and it will take significant time and effort to redo the work when the government realizes this work is important again. How should we talk about health equity? This is hard because the words “equity” and “DEI” are currently very politically charged. So whether you’re a public health professional, teacher, or friend, how we talk about this topic matters. The right framing can help people who might otherwise be skeptical see why health equity research is important and deserves funding. Here are some suggestions to help your conversations: Choose your words strategically: Who are you trying to reach with your message? Are they likely to be resistant to terms like “diversity” and “equity”? If so, find alternative words to use to still get the message across. It is frustrating to be in that position, but the goal of improving health is too important not to try to make inroads. Sometimes simply reframing can help the message reach those who need to hear it. Focus on the problem: The terms “health equity” and “DEI” are abstract. Make it more specific. For example, discuss differences in maternal death or ways to improve health outcomes in rural communities. These still have equity at their core but will likely be better understood by those you’re talking with. Focus on systems: Disparities exist, but if they are communicated poorly, people can mistakenly think the issue is the individual’s fault. Disparities are largely driven by failures of the system—such as lack of access to health care and a long legacy of racism. When discussing the disparities, frame them around these systemic issues to ensure blame isn’t placed on the individuals impacted. Tell stories: Personalize these policies by using stories from those impacted that connect to the data you’re trying to convey. This helps make the policies and outcomes more concrete and meaningful. Bottom line Some communities end up sicker than others. That’s just the facts. We can argue about the best way to do that research, but canceling it simply because it may be linked to DEI doesn’t make anyone healthier. It just leaves communities like the Hill district behind. And in the end, it causes us all to move backward in our efforts to improve health in this country. Love, EM Big thanks to MacKenzie Isaac & Legairre Radden, who reviewed this piece and generously shared their expertise and lived experience to help improve it. Dr. Liz Marnik, PhD, is Executive Director of The Evidence Collective and a science communicator and immunologist working at the intersection of public trust, science, and public health. To discuss communication training on topics like health equity and storytelling, email Liz at liz@yle.health or learn more on our website. Your Local Epidemiologist (YLE) comprises a team of experts, ranging from physicians to immunologists to epidemiologists to nutritionists, working together with one goal: to “translate” ever-evolving public health science so that people are well-equipped to make evidence-based decisions. The YLE suite of newsletters reaches over 475,000 people across more than 132 countries. This newsletter is free to everyone, thanks to the generous support of fellow YLE community members. To support the effort, subscribe or upgrade below: Your Local Epidemiologist is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe
Black politics needs more than better voting maps
The modern voting rights movement has become a tool to preserve the Black politician’s job, particularly the establishment Democrat.
Data-Driven EnviroLab team maps the heat - College of Arts and Sciences
The lab’s researchers use the data to identify hotspots and find ways to cool them down.
Google seemingly confirms plans to kill ChromeOS in 2034
Google support maps out how Googlebooks can take over where ChromeOS left off.
New 'Pokémon Winds and Waves' Leaks Fill Major Gap Left by Game Freak's Silence
Including gameplay, maps, and Elite Four character models
John Mayer maps Sphere shows with innovative format
John Mayer will hit the Las Vegas Sphere in the spring for shows that showcase his music in three forms.
New framework maps the complex link between psychological status and cardiovascular health
CVD remains the leading cause of death worldwide, while the global burden of mental disorders continues to rise.
Uncovering the Valleys Hidden Below Greenland’s Ice
A new map of the terrain beneath the Greenland Ice Sheet links hundreds of valleys that previous maps missed or left fragmented.
Across the South, Black voters weigh a new political reality
New voting maps in the South have sparked a wave of grassroots activism following a major Supreme Court ruling.
NFL Week 3 TV coverage maps
There are 15 games remaining on the NFL schedule in Week 3. Where and when will they air?
TV maps for Week 3 of 2026 NFL games
There's a full slate of NFL action Sunday on CBS and FOX. Here's a look at the Week 3 TV coverage maps.
Which games are Fox, CBS broadcasting? NFL Week 3 coverage maps
Which NFL games will be broadcast in your region in Week 3? Here are the coverage maps for Sunday's action.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf [30] M. Lofrano, X. Chang, H. Oprins, and Z. Tokei, “Mitigating the thermal bottleneck in advanced interconnects,” imec, Sep. 28, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/mitigating-thermal-bottleneck-advanced-interconnects [31] S. Bair, “Intel at ISSCC 2025: Navid Shahriari invited talk, eight papers, forums, panelist & product details,” Intel Community, Feb. 19, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://community.intel.com/t5/Blogs/Tech-Innovation/Edge-5G/Intel-at-ISSCC-2025-Navid-Shahriari-Invited-Talk-Eight-Papers/post/1667592 [32] D. Chandra, E. Potladhurthi, D. R. S. Reddy, and K. S. Rengarajan, “Tunable negative bitline write assist and boost attenuation circuit,” U.S. Patent Appl. 20160203857 A1, Jul. 14, 2016. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20160203857A1/en [33] Synopsys, “Advantages of firmware-based training in high-speed DDR IP,” Synopsys IP Technical Bulletin. Accessed: Sep. 14, 2026. [Online]. Available: https://www.synopsys.com/articles/firmware-based-training-ddr-ip.html [34] N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “CACTI 6.0: A tool to understand large caches,” Hewlett-Packard Laboratories, 2009. Accessed: Sep. 14, 2026. [Online]. Available: https://users.cs.utah.edu/~rajeev/cacti6/cacti6-tr.pdf [35] Intel, “Intel Tech Tour 2024 Lunar Lake AI hardware accelerators,” Doc. 824436, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/824436/2024_Intel_Tech%20Tour%20TW_Lunar%20Lake%20AI%20Hardware%20Accelerators.pdf [36] Y.-H. Chen, J. Emer, and V. Sze, “Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks,” in Proc. 43rd ACM/IEEE Annu. Int. Symp. Comput. Archit. (ISCA), Jun. 2016, pp. 367–379, doi: 10.1109/isca.2016.40. [37] Intel, “Introduction to the Xe-HPG architecture,” Doc. 758306, Nov. 4, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/developer/articles/technical/introduction-to-the-xe-hpg-architecture.html [38] Intel, “Core Ultra processors Series 3 for the edge,” Doc. 855291. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/855291/Intel%C2%AE%20Core%E2%84%A2%20Ultra%20Processors%20Series%203%20for%20Edge%20Overview_2.pdf [39] Intel Foundry, “Foveros technology brief,” Doc. 366411-001US, Feb. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-07/foveros-25d-product-brief.pdf [40] D. Das Sharma, “UCIe: Building an open chiplet ecosystem,” UCIe Consortium, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.uciexpress.org/_files/ugd/0c1418_c5970a68ab214ffc97fab16d11581449.pdf [41] Intel, “Intel launches Intel Core Series 3 processors,” Intel Newsroom, Apr. 16, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-launches-intel-core-series-3-processors-changing-the-game-for-everyday-computing.html [42] Intel, “Core Series 3 launch press deck,” Apr. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://download.intel.com/newsroom/2026/Intel-Core-Series-3/Intel-Core-Series-3-Launch-Press-Deck.pdf [43] Intel, “Intel outlines architectures for agentic AI at Hot Chips 2026,” Intel Newsroom, Aug. 24, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-outlines-architectures-for-agentic-ai-at-hot-chips-2026.html [44] Intel, “Intel accelerates process and packaging innovations,” Intel Investor Relations, Jul. 26, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-21-224438/d199788dex991.htm [45] Intel, “Intel reports third-quarter 2021 financial results,” Intel Investor Relations, Oct. 21, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/1505/intel-reports-third-quarter-2021-financial-results [46] Intel, “3rd generation Intel Core processors bring exciting new experiences and fun to the PC,” Intel Investor Relations, Apr. 23, 2012. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/577/3rd-generation-intel-core-processors-bring-exciting
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The core anti-Pangram constituency is phony writers
Welcome to The Closing Argument, our verdict on the news, plus everything The Argument published and appeared in this week. The Verdict, by Kelsey Piper A lot of people hate AI for drowning the internet in slop and displacing human creatives. You might think that these people would be thrilled by a program that can identify and flag AI-generated work. But many people who hate AI also hate Pangram, an impressively accurate AI detector that produces very few false positives, according to high-quality independent research. This loathing found its most recent expression in a bizarre Wired article that amplifies a wide range of false arguments from Pangram skeptics: that AI detectors are racist (they’re not) or ableist (they’re not)1 or don’t work (this one does)2. Rather than starting from the premise that it would be really valuable to have a working AI detector and scrutinizing Pangram to make sure it lives up to that promise, the article starts from the premise that Pangram obviously has bad vibes and sets out to discover why. (One answer: The CEO microwaved lunch during an interview!) Why aren’t writers who resent Pangram more eager to distinguish themselves from posters who are having ChatGPT ghostwrite all their work? There are a few different things at play, but I think one key dynamic is this: These are often the same people. A core constituency for arguments like Wired’s is “writers” who are using AI to write their posts but resent this fact being made public. They stand to lose from AI detectors because AI detectors call them out. Share When Substack announced a partnership with Pangram, a sizable fraction of the platform’s authors rose up in outrage. Some people had experience with other AI detectors that didn’t work, and some felt that AI writing ought to be encouraged — both of which are fair enough. But the fury was fueled by authors passionately insisting that Pangram kept wrongly accusing them on almost every post they published. Pangram can be wrong, especially on short passages. But in the overwhelming majority of cases where Pangram looked at a whole blog post rather than a single paragraph, the program correctly detected work as AI. Even if we can’t be 100% sure in any individual case, we can notice the trend in the aggregate. Wired quotes Sam Illingworth, a professor of critical AI literacy at Edinburgh Napier University, who said, “I don’t think [AI detectors] work. … I think that detectors are prejudiced against certain people.” This spring, he said that he used AI for research and editing; this summer he acknowledged that in addition to research and editing, he also uses it “now and then for a turn of phrase I keep.” Pangram informs us that most of his posts are 100% AI-written (some are mixed AI-and-human) and that 100% AI-written posts started appearing last year. The favorable interpretation is that, as someone whose recent work Pangram consistently mistakes for AI, Illingworth sees Pangram’s flaws firsthand. The unfavorable interpretation is that the tool’s credibility trades off against his own, because its account of who writes his posts is not consistent with his. Illingworth is not alone in insisting the detector does not work. “It’s a Monday night in late July, and I’m pasting my own Substack draft into an AI detector for the first time. Not because I’m worried. Because I’m curious. I wrote every word of it myself, the way I write everything, out loud in my head first, in a rhythm that still carries the accent of a language I learned to think in before I learned to write in this one,” begins one Substack post by an author indignant that Pangram flags her writing as AI. “That’s the part I had to sit with before I could write this.” If you, like me, have worked with AIs a lot, you won’t even need Pangram there. The author of that piece is AI. It is obviously AI! I checked 10 other posts on the blog, and they were also obviously AI! “I have spent 22 years as an award-winning author and essayist. And now this bullshit tool that learned from MY writing is going to accuse me of plagiarism,” popular Substack writer Carlyn Beccia wrote in an anti-Pangram post. “For the last and final time, AI DETECTORS DO NOT WORK.” Here’s what her writing sounded like in 2020: “Most success stories revolve around one person who believed enough in you to say — give it a try. We call these people muses, but they are so much more than that. They are the strong man giants whose shoulders we stand on so we can see the horizon. Throughout the editing process, I am sure my editor felt less like a giant of greatness and more like Atlas with the world on her shoulders.” Pangram says it was 100% human-written. (So were other articles of hers in 2020.) And here’s what it sounds like now: “And then there is the reshuffling, which sounds like paperwork until you remember that empires have always loved paperwork. The Trump regime recently moved special education oversight from the Education Department to HHS. That is not a minor bureaucratic transfer. It changes the frame.”3 Pangram says this is mostly AI. I am not convinced that Pangram is wrong. In my own experience, Pangram is very effective on long texts — if it marks a long essay as AI, the essay was either written by AI or deliberately written to sound like AI. On tweet-length or paragraph-length texts, it’s not perfectly reliable. It seems to work just as well for non-native English speakers as for native speakers. While I have seen dozens of claims of pre-2022 text returning a positive result on Pangram, I have tried repeatedly to corroborate those and have never once succeeded. To be clear, I’m absolutely not saying that complaining about Pangram suggests a writer is a cheat. There are plenty of other concerns. Most are mistakenly premised, such as the false claim that Pangram trains on work you put into it, but others are reasonable: It’s unreliable on sufficiently short text segments; it creates an internet witch-hunt mentality when there are defensible uses of AI; people who are open about their AI use are sometimes blamed, when the only people really doing something wrong are the ones who hide it; and it isn’t perfect, so a single positive result shouldn’t be taken as decisive proof of misconduct. I’m happy to concede that Pangram is imperfect and possible to over-rely on. If an author’s posts are mostly non-AI and one scans as partially AI, this could be a mistake. It’s also possible to defeat Pangram with intentional effort. If you think we need something more robust and more reliable, fine! But if you don’t like AI and don’t like Pangram, your attitude really ought to be that it’s a shame that our existing tools for AI detection are imperfect, and it’s important to invent better ones. If your stance is instead that AI is evil and so is looking for AI, then ultimately you’re contributing to the sloppification of the internet. You’re making it harder for people who write their own text to distinguish themselves, and providing cover for authors who are definitely not writing their own text. Subscribe Top stories this week, by Kobe Yank-Jacobs Commentators often worry that the decline of reading could mean the decline of liberal democracy — but deliberative governance actually predated widespread literacy. This week, Maibritt Henkel pointed out that many liberal cultures thrive on a culture of raucous, interactive debate, which can happen in-person as easily, if not more so, than in text. Read on, dear reader, to learn more. It may actually cheer you up: [ ](https://www.theargumentmag.com/p/reading-wont-save-liberalism) [ Reading won’t save liberalism ](https://www.theargumentmag.com/p/reading-wont-save-liberalism) Maibritt Henkel · Sep 1 [ Read full story ](https://www.theargumentmag.com/p/reading-wont-save-liberalism) It used to be bad to downplay climate change (if we mean denying its reality). Today, it’s actually good to downplay climate change (if we mean keeping the issue out of political fights so we can make real progress). This counterintuitive view is called “climate hushing,” and contributor Alex Trembath argued that it’s the key to enacting good policy going forward. Get up to speed on the latest in climate politics: [ ](https://www.theargumentmag.com/p/we-wont-stop-climate-change-by-talking) [ We won’t stop climate change by talking about it ](https://www.theargumentmag.com/p/we-wont-stop-climate-change-by-talking) Alex Trembath · Sep 2 [ Read full story ](https://www.theargumentmag.com/p/we-wont-stop-climate-change-by-talking) Canada’s Prime Minister Mark Carney is standing up for the forces of liberalism against Donald Trump’s assault on our closest ally. So, why is one prominent left-wing commenter attacking Carney? Columnist Matthew Yglesias explains: [ ](https://www.theargumentmag.com/p/when-economic-liberty-means-central) [ When "economic liberty" means central planning ](https://www.theargumentmag.com/p/when-economic-liberty-means-central) Matthew Yglesias · Aug 31 [ Read full story ](https://www.theargumentmag.com/p/when-economic-liberty-means-central) 🌟Abundance Wins of the Week🌟 Shout out to my home state of California, whose legislature passed two housing bills this week. One requires a housing density minimum in transit-oriented areas of the state’s most transit-rich cities (Los Angeles, Sacramento, San Francisco, Oakland, San Jose, San Diego, and Long Beach). Another bill closes two common loopholes used by third parties to delay housing projects, including an opportunity to challenge maps of a given lot created by the developer after a project has been approved. Shout out to our big-state rival, Texas, where pro-housing SB 785 took effect this week. The new state law requires municipalities to have at least one district permitted for manufactured housing without a special permit. This will promote zoning changes in 44% of municipalities. The company Fervo Energy signed a deal with Google for what is set to be the world’s largest enhanced geothermal facility, proving a technology can work at a scale that could be crucial to a decarbonized, energy-abundant economy. Share Worth watching… This week, forecasting legend Nate Silver joined Jerusalem, Matt, and Jeremiah on a crowded episode of the pod. It was a party. And speaking of parties, our round table debated the factional lines within the Democratic Party: Is it possible to be center-left and also anti-establishment? Watch or listen to find out: The Rio Grande Valley in Texas is one of the areas that swung hardest toward Trump in 2024, but musician Bobby Pulido is running to flip it back. Right now, The Argument/Split Ticket’s model has him running 1.1 points behind his Republican opponent in a district Trump won by 18 points. Tune in to find out how he differs from national Democrats and what he thinks he can to do win this seat. On Thursday, Bernie Sanders was among the first politicians to call for a ban on superintelligence. My guest this week, Andrea Miotti, has been lobbying to ban superintelligence for several years, most recently in the U.K., U.S., and Canada. I asked him how he gets legislators to take speculative risks seriously, and we dug into what plans might look like to actually pass a ban. Listen to learn more: What’s News with The Argument The Argument recommends, by Kobe Yank-Jacobs If we ever lose track of Justin Zuckerman, I’ll have the team split up and check all the movie theaters in the city. I’m shocked (and a little jealous) at how often he gets out to see good cinema. This week, he brings us It Ends, a “horror-ish movie,” which he described as a “Gen Z Waiting for Godot.” I was intrigued before he added that it was “funny, dark and existential” — at which point I was fully locked in. I guess I also had existential themes on the mind this week. One morning, a single line from a poem I read long ago just came to me: “Is death a stretch of time in which a life is just a flash?” The poem is called “From 20,000 Feet” by Heather McHugh. I suggest the version in The Vintage Book of Contemporary American Poetry, which, by tradition, my best friend and I always bring backpacking, extra weight be damned. We’ll stay thematically dark for just one more rec from senior editor John Robert Thomason, whose upcoming trip to Baltimore reminded him to suggest Michael Clune’s memoir White Out (about being addicted to heroin in Baltimore in the 1990s). Ben Lerner’s blurb called it _“_Disturbing, brilliant, hilarious—it’s as if Proust had written Jesus’ Son.” John told me this “seems accurate, with the caveat that I’ve never read Proust.” I, personally, have also shelved Proust until retirement. At this point, I was a little concerned for the team since all of us tossed out such psychologically grim material — maybe we’re all down about the end of summer — but thankfully, at least a few of us were into more upbeat selections. Milan Singh recommended Made In’s 5-quart stainless clad saucier, suggesting he had some fun in the kitchen. Jeremiah Johnson asked if he could recommend yet more Carly Rae Jepsen. Once denied, he offered up Game Changer instead_,_ calling it “the most wildly creative game show, maybe in the entire history of the genre.” Eli Richman mentioned _Lucky, “_a B-tier show with an A-tier cast and an S-tier theme song.” I suppose he was recommending the song, Horns of a Bull. Still, despite these cheerier recs, I couldn’t help but be concerned that we were subconsciously worried about racing toward summer’s end — the end of swim trunks and splashing around. Then a message landed reminding me of the three-day weekend to come. A whole extra day for sunshine. One more swim in the lake. I was grateful this called to mind yet another line from a poem, one by Mary Oliver, the patron saint of every gorgeous summer day (and about whom a documentary is now out). Speaking to God in the poem “Thirst,” she wrote: grant me, in your mercy,a little more time. Love for the earthand love for you are having such a longconversation in my heart. We have merch! We have quarter-zips, keychains, hats, and stickers. Each one is a great conversation starter in its own way. Buy them here. Subscribe More to read: [ The Opening Argument ](https://www.theargumentmag.com/p/seeing-like-an-elite)[ Seeing like an elite ](https://www.theargumentmag.com/p/seeing-like-an-elite) Kobe Yank-Jacobs · Sep 4 What do Americans hear when they watch Sen. Bernie Sanders or Vice President JD Vance rail against the elite? Are they thinking of right-wing tech billionaires? Imperious college professors? Liberal magazine writers? [ Read full story ](https://www.theargumentmag.com/p/seeing-like-an-elite) [ The Weekly Scroll ](https://www.theargumentmag.com/p/god-is-back-on-the-timeline)[ God is back on the timeline ](https://www.theargumentmag.com/p/god-is-back-on-the-timeline) Jeremiah Johnson · Sep 5 This week, we’re talking about Substack’s new religious debates, the continuing MAGA influencer scandal, how to retire from YouTube, and aura battles. [ Read full story ](https://www.theargumentmag.com/p/god-is-back-on-the-timeline) 1 This was a legitimate thing to worry about, but doesn’t seem to be a problem given the actual technology: Marijke Van Vlasselaer, Filip Van Droogenbroeck, and Bram Spruyt’s 2026 paper looks at whether Pangram is less accurate when evaluating the work of non-native speakers of English. It isn’t. That’s because Pangram isn’t really looking at how “unusual” a piece of writing is but whether it has the characteristic patterns of LLMs. The Wired article makes an odd gesture at a different Pangram-is-racist argument. There were several controversies this summer during which upcoming books were canceled after being discovered to be AI-written: “The three novels mentioned earlier — Shy Girl, Daggermouth, and Call Me, easily publishing’s biggest AI-detection scandals — were all written by writers of color.” But come on! As Zvi Mowshowitz put it: “They were not primarily written by people of color. They were primarily written by AIs.” That’s the whole problem! And as my colleague Jeremiah Johnson recently observed with respect to Cambridge’s Arday scandal, a community being unwilling to call out fraud if it’s perpetuated by people of color is not an anti-racist tendency; it is ultimately quite racist. 2 Many non-Pangram detectors don’t work, but many possible airplane designs also don’t work, and no one considers this a general argument against aviation; the thing that matters is whether any detection works. 3 The phrase “empires have always loved” mysteriously became all the rage in the last few years. See here, here, here, here and here. Before 2025, the only use of that phrase I have been able to find is a single Tweet. The logic of the sentence, too, is incoherent in an AI-characteristic way. “...sounds like paperwork, until you remember that empires have always loved paperwork”? Does remembering that make it sound less like paperwork? It’s a craft-ful sentence, but what is it actually saying??
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Apple is following Google Maps, after President Donald Trump ordered the federal government to change the name of a Great Lake.
Colorado redistricting limits measure heads to November ballot
A proposed constitutional amendment that would prohibit Colorado’s congressional maps from being redrawn outside of election cycles has qualified for the November ballot, according to the Secretary of State’s Office. Under Initiative 256, redistricting changes for the 2028 election and beyond would be prohibited unless approved by the Congressional Redistricting Commission and the Supreme Court. […]
Trump Personally Bullying Apple to Make It ‘Lake America’
Google Maps has already surrendered on the president’s ridiculous name change, but he isn’t satisfied.
Google is getting flak for changing Lake Ontario name to Lake America
Canadian politicians are also scrubbing government websites that embed Google Maps to ensure the lake is labeled Lake Ontario.
Google Maps changes Lake Ontario to ‘Lake America’ for US users after Trump order: 'It's official!'
Google Maps has updated Lake Ontario to “Lake America" for U.S. users following Trump’s executive order and the federal government’s official name change.
Google Maps adds 'Lake America' as Ford compares change to 'SNL' skit
"No one's going to call it Lake of America. It's been Lake Ontario for hundreds of years," Ontario Premier Doug Ford said.
Ads have landed in Apple Maps, and they are as bad as expected
When we ran a poll last month, the overwhelming majority of 9to5Mac readers agreed that Apple should exit the ad...
The Warhammer 40,000 August Update – Everything you need to know
New updates for points, maps, and detachments.
Apple Maps Ads Are Here, and There's No Way to Turn Them Off
Ads in Apple Maps are live in the United States and Canada, which means iPhone and iPad users will see them when searching for locations and when viewing Suggested Places. Apple announced plans to bring ads to the Maps app in March, and said the feature would roll out starting in late summer. Apple confirmed to 9to5Mac that ads began showing up for users over the last few days, with ad placement to ramp up in the coming weeks.
Apple Maps launches ads on iPhone, here’s what’s new
Apple has officially launched ads in Apple Maps, with the rollout ramping up in the coming weeks. Here are the details.
Call of Duty: Modern Warfare 4 – Inside the Maps and Movement of Multiplayer
Call of Duty Season has officially kicked off with Call of Duty: NEXT, along with the first of two beta weekends for Call of Duty: Modern Warfare 4, giving us our first hands-on with the newest maps, combat mechanics, and more.
‘GTA VI’ Leaker Drops Even More New Footage, Reveals Motivations
'GTA VI' is currently suffering from a number of leaks from a specific leaker, revealing gameplay, maps, systems and more.
Live results: Florida primary election
See Florida election results and maps for the 2026 primaries.
Disinformation tracker maps declining confidence in science and public health
When Russia launched its full-scale invasion of Ukraine, false claims about “US-run biolabs” began circulating almost immediately through Russian state
Republicans won the redistricting competition. Don't tell that to this California congressman
President Donald Trump last year told GOP-controlled states to redraw their maps before this year's midterm elections to increase the number of winnable seats for Republicans in order to help the party hold onto the U.S. House.
Michigan Gov. Gretchen Whitmer: Michigan and KY are ‘roadmaps of hope’
“It’s states like Kentucky and Michigan that are showing that we don’t have to live like this anymore,” Whitmer said in Lexington Saturday.
City breaks ground on MAPS 4 Mental Health Crisis Center
OKC’s summer of groundbreakings continued Monday as officials broke ground on the upcoming Robert Ravitz Crisis Center, a central project of MAPS 4
Radio telescopes help scientists map molecules in space and uncover where and how stars form
Interstellar maps can help scientists find patterns that tell them about fundamental chemical processes in the cosmos.
Live results: Connecticut primary election
See Connecticut election results and maps for the 2026 primaries.
Live results: Vermont primary election
See Vermont election results and maps for the 2026 primaries.
'Every life is worth another chance': OKC breaks ground on $12 million mental health crisis center
Oklahoma City leaders broke ground on a new mental health crisis center funded through MAPS 4, designed to provide critical services and ease the strain on emergency rooms, jails and first responders.
New Science Maps Asia’s Shark And Ray Hotspots And Exposes Major Conservation Gaps
Scientists mapped 122 Important Shark and Ray Areas across Asia covering ~1 million km², revealing that while these habitats support 121 species (many threatened), over 94% of them still fall outside marine protected areas.
How Does Google Maps Know A Business Is Busy?
Google Maps can tell you how busy many businesses are. It's a convenient feature, to be sure, but how is the site able to provide that information?
Vandalism, populism and a rise in state tourism: CT politics news
Murphy maps out his vision of ‘economic populism.’ State tourism had a big year. And vandalism at the Nathan Hale Homestead in Coventry.
New official 30th anniversary Quake mission pack adds new maps and mechanics
19 new maps continue the story from MachineGames' other campaign additions.
Tesla Rolls Out New Maps Update in North America
The new map data package brings updated street layouts, revised speed limits, and points of interest across to Tesla vehicles across the continent