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First Look: The Voisin Aerosport, Albishorn's Retro-Futuristic Take on the Dress Watch
Expanding beyond tool watches, Albishorn introduces a 1930s-inspired chronometer influenced by Gabriel Voisin, the Voisin Aerosport.
100 buses long: Scientists map one of the world's largest known coral colonies
A huge coral colony stretching more than 1.5 kilometers (0.93 miles) along the outer reef of the Cocos (Keeling) Islands has been identified by researchers, making it one of the largest known coral colonies ...
High school sports roundup for Nov. 7, 2026
Cross Country 3A State Championships Sun Willows Golf Course, Pasco 5000 meters Boys team scores: 1. Gig Harbor 107 2. Bishop Blanchet 110 3. Mt. Spokane 117 4. Shorewood 166 […]
Rare fifth-century burials of Germanic chieftains with dazzling weapons and warhorses discovered in France
Archaeologists found a small cemetery full of high-status burials, two of which may be the graves of Germanic chieftains.
Scientists Discover Something Unexpected 90 Kilometers Beneath Earth
A rock from Papua New Guinea was hotter than expected during its descent into Earth, challenging models of a process that influences earthquakes, volcanoes, and climate. Earth recycles its own surface. In regions called subduction zones, one tectonic plate, a vast slab of Earth’s outer shell, sinks beneath another as the plates collide. These zones
Scientists discover new jellyfish species in waters off Alicante in Spain
The Mediterranean Sea still holds species unknown to science. One of them is Copula lucentia, a tiny jellyfish measuring just a few millimeters. Discovered off El Campello, in Alicante, it was formally ...
In 2023, Scientists Diving 4,000 Meters In The Clarion-Clipperton Zone Spotted A Squid Doing Something We Had Never Seen Squid Do Before
I'll give you a clue: it wasn't this way up.
The New Serica 8315 Travel Chronometer Golden Green Brings A Different Shade Of Character
✓ Jorg goes hands-on with the Serica 8315 Travel Chronometer Golden Green ✓ Quite possibly the best version yet ✓ Read it here! ✓
When papers become currency: a Chinese debate about trust in science
Last Saturday, 31 October, I went to the University of Hong Kong’s Beijing Centre for its Talent Forum. It was the fourth stop in the series this year, following events in Shanghai’s Zhangjiang, Shenzhen’s Qianhai, and on HKU’s main campus. The programme covered a remarkable distance in one afternoon. HKU’s Xiao-Jing Wang discussed computational neuroscience, intelligence, and the prefrontal cortex—before even delivering his inaugural public lecture to students back in Hong Kong. His colleague Bing Zhang took us from the Big Bang to artificial intelligence. Tsinghua’s Xue Lan asked how AI might reshape the institutional infrastructure underpinning higher education. There were lively panels featuring industry leaders from JD.com, Xiaomi, Haier—and Kaiser Y Kuo on the closing panel discussing innovation and international connections. I cannot pretend to have followed every detail of the brain models or the astrophysics. The talk that stayed with me was closer to something we have covered before: Zhou Zhonghe 周忠和 on papers, evaluation, and scientific trust. Zhou is a palaeontologist, an Academician of the Chinese Academy of Sciences, and an international member of the US National Academy of Sciences. He is also editor-in-chief of The Intellectual (知识分子), China’s leading science commentary platform. His subject was uncomfortable enough for a room full of successful academics: what happens when the system for recognising good science starts rewarding something else? Part of my interest came from our sister newsletter, The East is Read, which covered the controversy around “Geng Tongxue” in May. A PhD dropout from Beihang University, Geng has publicly challenged papers by prominent researchers through detailed online allegations of manipulated images and fabricated data. At Tongji University, an investigation into a challenged Nature paper found academic misconduct, and the dean of its life sciences school was removed. The affair brought doubts about academic integrity well beyond laboratories and university committees. How could someone outside the established hierarchy spot problems in papers that had passed through prestigious journals and institutions? And what, exactly, had all that prestige guaranteed? Zhou approached these questions through two essays published in July by The Intellectual: one by Wang Xiaodong, director of the National Institute of Biological Sciences, Beijing, and a response by Wang Liming, of Shanghai’s Shangsi Institute of Natural Sciences. Both began with the controversy over Geng. Their arguments deserve a wider audience, so I want to put parts of them alongside what Zhou said on Saturday. Wang Xiaodong’s starting point is evolution. A research system selects for the behaviour it rewards. Grants, jobs, journals, talent programmes, and prizes collectively determine which scientists prosper and which practices get passed down from advisors to students. “Whatever the system rewards is what it will evolve to produce,” he writes, citing the ancient Chinese saying: The King of Chu loved slender waists, and many in the palace starved to death. That is a more demanding diagnosis than saying there are dishonest people in science. Punishing a fraudster does not change the selective environment that made a particular kind of research profitable. His account also gives scientific success an awkward role in the story. As Zhou put it on Saturday, science became a victim of its own success. Once research became central to industry, national power, and economic growth, universities and laboratories expanded, and public money followed. That created an administrative need for rapid decisions: who should get the next grant, the next laboratory, the next appointment? The difficulty is that the true value of a discovery may take years or decades of testing and building to become clear. Resource allocation cannot wait that long. Publication counts, journal prestige, impact factors, and citations therefore become convenient ways to make an instant judgement. “The real problem is not that these indicators have no value,” Wang Xiaodong writes, “but that they are trying to answer a question that only time can answer.” Telling administrators simply to stop counting papers will never be enough. They still have budgets to distribute and appointments to make. Something has to replace the shortcut. Zhou described the consequences inside publishing. Papers acquire ever more requirements: a complete story, polished presentation, extensive datasets, and accessibility to readers beyond the immediate field. Individually, those demands sound reasonable. Together, he warned, they produce formulaic “eight-legged” papers 八股文 and rigid reviewing, while genuinely original or non-consensus work struggles to get past journal editors—some of whom wield immense gatekeeping power despite having limited laboratory experience themselves. Meanwhile, the demands for sprawling, “complete” narratives have fuelled a wider replication crisis. Wang Xiaodong uses a mahjong metaphor to describe the result: put the complex papers published by the exact same lab over several years side by side, and they often look like “Thirteen Orphans” (十三不靠)—every tile completely unrelated to the next, and none of them reproducible by outsiders. Zhou also spoke frankly as an editor who has trouble finding reviewers. Everyone wants someone else to review their work; qualified senior researchers have little time to return the favour. The labour is anonymous, unpaid, and brings almost no institutional recognition, so it increasingly gets passed down to postdocs and graduate students. And while anonymity protects reviewers from rank and personal favours, hyper-specialisation means an author’s most qualified reviewer is often a direct competitor, shielded from accountability. The protection and the problem coexist. Wang Liming takes the argument a step further. The decisive change, in his essay, is the instant conversion of academic honour into material resources. Once a paper can be cashed in for funding, a job, students, commercial investment, or even a company valuation, scientists are alienated from their work: they must keep minting this “research currency” to keep their teams alive. He is careful not to romanticise the past. The old world of gentleman scientists—financially independent figures like Boyle and Darwin who needed nothing from external funders—was also a closed club that excluded people without inherited wealth, women, and much of humanity outside the West. Professional science allowed ordinary people, himself included, to become researchers. Nobody should want to undo that. The problem, in his account, is an exchange system that becomes too uniform and too difficult to correct. His most pointed Chinese example is the “hat” (帽子): the prestigious talent designation that brings continuing access to money, laboratory space, students, and institutional influence. “If papers are the circulating currency of the research system, then a ‘hat’ is a bond that pays interest over the long term,” he writes. A paper at least requires another round of peer review. A title in the Chinese context can lock in a judgement made years ago and turn it into permanent status rent, regardless of whether its holder is still doing good science. Here, official institutions hire, organise, and evaluate scientists. Unlike honours awarded by autonomous academic communities in the West, a Chinese “hat” blends non-scientist administrative power with state authority. Once granted, it turns a past judgement into permanent status rent that is nearly impossible to revoke—because taking a hat off would imply that official authority erred in putting it on. Both Wangs see China as experiencing, at compressed speed, pressures present across global science. Research expansion, rising investment, publication growth, and elaborate evaluation metrics arrived in China within two or three decades rather than two or three centuries. Zhou agreed with that international framing—noting that recent US White House science policy documents and the new president of the US National Academy of Sciences, a fellow palaeontologist who recently visited Zhou’s institute in Beijing, have raised strikingly similar warnings about consensus-bound peer review, short-term project grants, and the replication crisis. Still, Zhou emphasised that China’s traditional hierarchy, personal networks (guanxi), and the ethos that “a good scholar becomes an official” (学而优则仕) amplify those pressures at home. So what would change things? Here Zhou’s tone differed from the call for a revolution in scientific trust in Wang Xiaodong’s essay. As an evolutionary biologist, Zhou favoured patchwork repair (修修补补). Living systems survive through accumulated adjustments; dramatic mutations are usually fatal. Science cannot return to a small, slow-moving pastoral era, especially after the successive accelerations of professionalisation after the Second World War, the internet, and now artificial intelligence. But it can alter the local environment in which researchers work. He pointed to domestic experiments designed to support unconventional research and diversify funding, including Tencent’s New Cornerstone Investigator Program, the Xplorer Prize, and the Future Science Prize. He also mentioned participating in reviews for “major non-consensus projects” under the National Natural Science Foundation of China. One guiding principle he recalled was wonderfully direct: “Failure is allowed; corruption is not” (允许失败，不允许腐败). That distinction would mean quite a lot if taken seriously. An honest attempt that fails should not have to disguise itself as a success to survive an assessment. Wang Liming’s essay adds a sharp caveat to the optimism about new domestic funders. Multiple organisations do not automatically produce multiple ways of judging science. If the same pool of senior domestic scientists makes the decisions through the same two-round review procedures, it is still “fake diversity.” He argues for three distinct kinds of money: broad baseline funding governed by fair procedures; patient funding for questions that take ten years; and non-consensus funding based on individual taste, deliberately empowering a few genuine experts to make biased, contrarian bets on eccentric ideas that would inevitably be averaged out by a committee. Replacing one monopoly with another achieves little; a healthy ecosystem needs variance. Zhou’s proposals for publishing were similarly concrete: strip papers of their resource-allocation burden and return them to recording discoveries and establishing priority; separate dissemination from evaluation, as eLife and Peer Community In do; adopt more modular “micro-publications” and real-name endorsements; recognize the labour of editors and reviewers; and give replication work proper credit rather than treating it as an unpublishable dead end. AI makes every part of this debate more urgent—and Zhou wove it throughout his talk. In his own preparation, he used AI to survey the declining influence of academic monographs, noting how tools are already changing how scholars gather information. More fundamentally, he placed AI as the latest great acceleration in scientific history: just as the internet sped up the pace of research and tightened external resource pressures, AI is compressing the cycle again. In the essays Zhou cited, AI cuts both ways. Wang Xiaodong expects large language models to erase much of the English-writing disadvantage long faced by Chinese scientists, further swelling the flood of papers coming out of Chinese labs. Wang Liming sees AI accelerating both ends of the trust crisis: it lowers the cost of paper mills and fabricated images just as quickly as it lowers the cost of automated image forensics, data auditing, and code reproduction. “Whoever builds the verification layer wins,” Wang Liming writes. His proposed alternative to the static, packaged “story paper” is a continuously versioned “unit of discovery” containing a falsifiable claim, raw data, analysis code, experimental parameters, and an ongoing log of independent checks—where negative results and failed replications are recorded rather than buried. Zhou ended his keynote by bringing AI back to the question of scientific honour and credit. Citing a recent Intellectual discussion on “What AI Means for Mathematics” featuring Fields Medalist Deng Yu 邓煜—at a moment when AI is already batch-solving mathematical conjectures, as HKU Vice-President Lin Chen noted in his opening remarks—Zhou agreed that human researchers must remain the principal agents: AI is a tool that frees scientists from tedious calculation to think about deeper, messier real-world problems. Yet that partnership creates a thorny new evaluation problem. When a breakthrough is made with AI, what is the human contribution and what is the machine’s? And since AI models distil centuries of accumulated human scholarship, is it right that the credit and value flow so heavily to the private AI companies building the tools? The old struggle over how to assign scientific honour is acquiring a whole new layer. What I took away was a serious discussion of how science can remain trustworthy as its scale, incentives, and tools change. These were scientists with real standing inside China’s system questioning how that standing is produced, and proposing changes that would affect their own institutions and peers. That made the afternoon at HKU’s Beijing Centre worthwhile. At the close, Wang Feng, Director of Communications and Public Affairs at HKU, said the value of the forum series—which heads to Hangzhou in December and cities like Chengdu early next year—would lie in the real cooperation it helped bring about. The university has plenty to celebrate: this week it topped the QS Asia rankings for a second consecutive year, alongside its 11th-place position in the QS World University Rankings 2027. For me, bringing this debate to an audience beyond the people who review papers and allocate grants was a useful contribution. Share [ The East is Read PhD dropout’s exposé forces an academic fraud reckoning in China A former doctoral student turned blogger has shaken China’s academic establishment by publicly accusing prominent university scholars of fabricating data and manipulating papers, triggering investigations at several leading institutions and drawing rare attention from state media… Read more 5 months ago · 43 likes · 8 comments · Yuxuan JIA ](https://www.eastisread.com/p/phd-dropouts-expose-forces-an-academic?utm_source=substack&utm_campaign=post_embed&utm_medium=web&embedding_publication_id=47580)
Imaging Science Thesis Defense: A Step Towards Developing Digital Twins of Forest Environments with Terrestrial Laser Scanning | Events
Imaging Science MS Thesis Defense A Step Towards Developing Digital Twins of Forest Environments with Terrestrial Laser Scanning Zoom Link here Aisha Co Imaging Science MS Candidate Rochester Institute of Technology Abstract: Digital twins have become an increasingly relevant topic as we pursue accurate representations of the real world for planning, research, and even design purposes. This study focuses on the steps for creating digital twins of forest environments using sparse points from terrestrial light detection and ranging (LiDAR). Specifically, we developed geometric models of structural digital twins (SDTs) from leaf-off terrestrial laser scanning of real-world forests. Three algorithms were used to develop an approach to handle individual tree reconstructions for sparse point clouds, and they were tested and validated with a two-sample Kolmogorov-Smirnov statistic against an existing inventory of the RIT Nature Trail to evaluate the reconstruction’s fidelity. The key evaluation metrics included diameter at breast height (DBH) and height. The limited nature of available ground truth necessitated the use of an additional validation method using a PANGAEA open dataset, based on comparing DBH, height, and crown diameter against the dataset’s calculated measurements. Reconstructions were compared against per-tree reference values at two-point spacings for sixteen trees from the open BR07 dataset (PANGAEA); these specifications matched the collected RIT Nature Trail data and the scanner’s nominal spacing. On BR07, the proposed method had the lowest median DBH error among the methods that modeled every tree (1.28cm, 4.1%), and this error was nearly unchanged at the coarser spacing, while TreeQSM’s rose from 4.2% to 6.5% and AdTree overestimated DBH by 30% to 40%. Results show the proposed method understates the tree heights by 0.2m to 1.4m but contains the least error when estimating DBH. The proposed method was able to produce all 69 trees, while SimpleTree produced 49 and none at the 4.35 cm BR07 spacing. We concluded that the developed geometric model (digital) twins have significant potential to serve as both simulation and prediction tools. We recommend that future efforts focus on collecting per-tree ground truth measurements within the scanned plot and incorporating leaf-on scans. Leaf-on scans include representative foliage, which would add realism to the model and ecological function of the trees. Intended Audience: Beginners, undergraduates, graduates. Those with interest in the topic. To request an interpreter, please visit myaccess.rit.edu
Centuries-old cemetery helps scientists link climate shocks to Industrial Revolution disease
During England's Industrial Revolution, when the country's farming-based economy transformed into an industrial one between roughly 1760 and 1840, pollution, harsh working conditions, inadequate housing ...
Why curiosity and confusion are so important for scientists
For renowned physicist Asimina Arvanitaki, the pursuit of knowledge begins with curiosity and being in the dark. At a Perimeter Institute event in Waterloo, she talks to Nahlah Ayed about the importance of curiosity-based research, her own career, and the role of AI in science.
Fantasy Football Panic Meter: Ravens are in trouble going into Week 9 after latest Lamar Jackson injury
Fantasy Football Panic Meter: You shouldn't give up on Parker Washington after two subpar games
I skip the marathon for a 32-mile walk around Manhattan
I've never run a marathon, but I've walked the perimeter of Manhattan, about 32 miles, three times. I'm looking forward to doing it again.
Orlando Magic's Desmond Bane Highlights Team's Resilience Following NBA Cup Win
Desmond Bane’s 28-point explosion fueled a gritty rebound over Toronto, proving Orlando can thrive through injuries and adversity by leaning on perimeter depth and defensive connectivity.
Virginia and D.C. sue over Trump's arch, adding to legal challenges as government wants work to begin
There are now three lawsuits calling for a halt to potential work on a monument that would rise 250 feet on a patch of grass off the bridge that spans the Potomac River, connecting the city with Arlington National Cemetery.
Diplo: 'There's a big generational shift' of young people prioritizing health
Diplo talks with CNBC about hosting five-kilometer races across the globe branded as “Diplo’s Run Club.” The Grammy Award winner says, "There's a big generational shift right now, with young people realizing that they want to spend their time working on themselves and their bodies."
Rural US hospitals, collateral victims of Trump politics
Ninety miles (140 kilometers). That is how far residents of Fredonia, a small town in the central US state of Kansas, must travel for cardiology care in the event of a heart attack or stroke.
Oakwood Cemetery receives support from local business
NIAGARA FALLS, N.Y. (WIVB) — The first public cemetery in Niagara County is getting a helping hand from a local business. “Not everybody thinks about the cemetery or helping out at the cemetery, so it’s great to have volunteers and get people in here and see the other side of it,” Michael Baxter, director of […]
Do drivers convince themselves that speeding is OK? AAA explores
A recent survey of drivers found nearly half believe going a little bit over the speed limit isn’t really “speeding.”
Photo Essay: College of Science and Engineering Research Showcase
Fourth-year Mechanical Engineering major Jess Visaya and Fourth-year Mechanical Engineering major Dorette Pirie show off their soft robots. The robots are made to mimic worms, whose bodies bunch up before extending to propel themselves forward. The robots use pneumatic actuators to make linear movement outwards. Visaya and Pirie set up two of their worms with syringes attached to tubing which was then threaded through the end cap into the worms. Visitors to their station were encouraged to race the two worms by pumping the attached syringes. Third-year Biochemistry major Ira Evetts worked in Dr. Christopher Whidbey’s lab studying the vaginal microbiome, in an attempt to better understand the different microbes that build it up and how it affects health outcomes. Evetts’ research was specifically focused on lactobacillus iners, one of several bacteria naturally present in a healthy vaginal microbiome, and methylation systems. Fourth-year Mechanical Engineering major John Diesko Boehm and Fourth-Year Mechanical Engineering major Ian Agopsowicz hold up their “DAQMobile.” They built their project, a modified RC kit car, to help teach mechanical engineers about circuits and electrical design through real-world application. Fourth-year Mechanical Engineering major Ben Murphy holds up his mole crab and crawfish-inspired burrower. Murphy wanted to imitate the motion of a crab’s legs through robotics, with the primary goal to “turn the rotation of one motor into four alternating legs that would successfully displace soil.” Murphy was inspired by works that take inspiration from the natural world, and he found mole crabs particularly interesting. Although a mole crab is at an advantage with its burrowing being underwater, thus the sand being fluidized and easier to displace, Murphy’s machine is able to successfully burrow three centimeters into the ground. Second-year Mechanical Engineering major and Physics major Arabelle Miller shows off her rubber gripper, inspired by kirigami and origami. She took a piece of rubber and strategically cut slits into it to make it fold the way she needed, then glued googly eyes to the front. The gripper is able to hold up to 38 times its weight, or 226 grams. Third-year Mechanical Engineering major Joonseong Park talked about how his project took an unused and broken 3-D printer and transformed it into a testing platform for soft robotic grippers. The former-printer was reprogrammed and had its extruder part modified to be a mount for the grippers. Park shows off some of the other grippers that can be attached to the testing platform. Park classified grippers into two large categories. The first set of grippers is designed to deal with small delicate objects with great precision, and the second is made to lift heavy or large objects. Third-year Mechanical Engineering major Jiashuo Liu set out with a goal to deploy free open-source AI models to pre-existing robots to integrate object recognition and retrieval and command. The models are used to process the data received from the robots’ cameras in order to detect certain objects and their locations. Fourth-year Mechanical Engineering major Cole Purohit focused on agricultural automation of raspberry picking. His project utilizes kirigami to make grippers to close around a raspberry when the two ends are pulled. “Nobody wants to eat a squished raspberry,” Purohit said. Fourth-Year Biochemistry major Mariel Nolan’s project focused on bacteria and proteins within the bacteria whose functions are unknown. Nolan’s research is finding a way to isolate those proteins with the ultimate goal of determining their functions. Fourth-year Mechanical Engineering major Kai Boydon and Fourth-year Mechanical Engineering major Evan Nguyen show off their project, which uses custom extensors to help with the rehabilitation of stroke patients. They compared their project to a “party-popper” in the way it unfurls itself when placed under a patient’s fingers, helping the stroke patient rehabilitate finger movement. Boydon shows off the testing rig built for their project. It works as a mount for their extensor, as a way to test against resistance. Their program inflates the extensor through an air pump, which then makes the extensor push against the bed whilst an arduino calculates the force created and air pressure associated with the force. Navigate Left Navigate Right
'Northville Cemetery Massacre' Gets 50th Anniversary Blu-ray Disc Release Dec. 15 from VCI Entertainment
Longtime independent film distributor VCI Entertainment on Dec. 15 will release the 1976 motorcycle gang classic Northville Cemetery Massacre on Blu-ray Disc, the film’s first-ever appearance on the high-definition format. The “Special 50th Anniversary Special Edition” features a brand-new 4K restoration from the best available film elements. Also, for the first time on any home … Continue reading "‘Northville Cemetery Massacre’ Gets 50th Anniversary Blu-ray Disc Release Dec. 15 from VCI Entertainment"
‘KUWTK’ showrunner claims Kim Kardashian had a ‘gun to her head’ during a 2018 trip to Africa because of Kanye West
‘Keeping Up With the Kardashians’ showrunner Farnaz Farjam claimed that Kim Kardashian had a ‘gun to her head’ during a 2018 trip to Africa because of Kanye West, per Jonathan Van Meter’s new book ‘Citizen Kim.’
Cowboy Space unveils 'Big Iron' rocket to launch 20,000 AI data centers
Cowboy Space aims to launch the 282-foot-tall (86 meters) Big Iron for the first time in late 2028.
NFL Panic Meter: Chiefs have to address their offensive issues now, before they regret it
Scientists discover Arctic sea ice loss could be far worse than predicted
Arctic winter sea ice could disappear much faster than scientists previously expected, according to new research using climate clues from 6,000 years ago. By comparing ancient ocean sediments with modern climate models, researchers found that future winter ice coverage may be roughly one million square kilometers smaller than earlier predictions suggested.
Detectives seek information about business conducted with Piedmont Memorial Park Cemetery
Detectives are seeking information from anyone who has conducted business involving the cemetery since January 2019.
This Switch 2 sequel accessory was a few millimeters away from being good
The right stick gets in the way.
Michigan's Jason Beck promised change, but numbers tell another story
Michigan football vowed to fix its perimeter run game or stop it, but the team continues to struggle on the edge.
Scientists Studied 865 Humpback Whales and Found They Grow Faster Than Expected
Despite decades of environmental change and population recovery, eastern Australian humpback whales appear to have maintained their historical adult size. Eastern Australian humpback whales grow at an extraordinary pace, reaching approximately 10.9 meters (35.8 feet) in length by age five. By six or seven years old, they have already attained about 90 percent of their
2026-27 Season Preview: Ruben Dominguez
The Spanish sharpshooter will provide Xavier a lethal perimeter threat.
Empire Towers perimeter lift brings relief to nearby Glen Burnie businesses
After three months of road closures and disruptions, the safety perimeter surrounding Empire Towers in Glen Burnie has officially been lifted, bringing relief to nearby businesses that have struggled to stay afloat.
NASA’s Swift Mission Ends, Leaves Behind Scientific Bonanza
NASA’s Neil Gehrels Swift Observatory has ended its science mission now that the spacecraft is orbiting less than 171 miles (275 kilometers) above Earth’s
OPINION: Miami Heat Should Target Free Agent Shooting Guard
Following a dismal long-range shooting performance on opening night, the Miami Heat could look for a veteran marksman to restore the team's perimeter threat.
Scientists discover dangerous water oscillations between Lake Varna and Black Sea
For years, pilots have observed strong and unusual currents in the 2.4-kilometer-long (1.5-mile-long), 300-meter-wide (984-foot-wide) canal connecting Lake Varna with the Black Sea. Maarja Kruusmaa, an ...
Theatre Guild presents ‘The Cemetery Club’ to end its season
PUNXSUTAWNEY — The Punxsutawney Theatre Arts Guild is staging “The Cemetery Club” on Friday, Oct. 23, and on Saturday, Oct. 24, at the Presbyterian Church of Punxsutawney, located on Union
Race for Tarrant County judge a barometer of region’s political dynamic, analysts say
ncumbent Republican Tim O’Hare faces Democratic commissioner Alisa Simmons in the race for Tarrant County judge.
Scientists Transplanted 306 Square Meters of Wild Salt Marsh Into The World's Largest Wave Machine And Let a Simulated Extreme Storm Rip
"We had to bring the salt marsh to the storm."
Scientists Transplanted 306 Square Meters of Wild Salt Marsh Into The World's Largest Wave Machine And Let a Simulated Extreme Storm Rip
"We had to bring the salt marsh to the storm."
Hundreds of graves buried beneath a Clearwater business despite a $7.5M settlement
A $7.5 million settlement is bringing a three-year legal battle over a historic Black cemetery in Clearwater closer to an end, while questions remain about hundreds of graves buried beneath a local business.
A massive asteroid slammed into the North Sea and unleashed a 330-foot tsunami
A decades-long mystery beneath the North Sea has finally been solved. Scientists have confirmed that the Silverpit Crater, buried 700 meters below the seabed, was created when a 160-meter-wide asteroid struck Earth roughly 43 to 46 million years ago. The violent collision blasted a towering curtain of rock and water 1.5 kilometers into the air and triggered a tsunami more than 100 meters high.
Are partisan politics even changing up our accents? They just might be, y’all
Vowels have become the latest players in partisan politics, a barometer of how beliefs and values fit within the old vs. new South.
The Meter: Foreign Business Ownership in MN
How many foreign-owned businesses operate in Minnesota?
Chernobyl’s Radioactive Debris Is Defying Scientists’ Expectations 40 Years Later
Some of Chernobyl’s radioactive debris is more resilient than scientists expected, offering clues to when the material trapped inside could escape into the environment. Radioactive dust still contaminates the soil around Chernobyl four decades after explosions scattered debris from the nuclear reactor in Ukraine in 1986. The fragments measure just 8 to 50 micrometers across
Scientists uncover 3 key brain pathways linked to lasting depression relief
Researchers have uncovered three brain pathways linked to lasting improvements in people receiving deep brain stimulation for severe, treatment-resistant depression. They also discovered that patients who failed to improve after two years shared a striking pattern: insufficient stimulation of a crucial brain connection. The findings suggest that millimeters in electrode placement could make a major difference in treatment outcomes.
Salt crystals could hold clues to life beneath Enceladus's ice
The ocean beneath Saturn's moon Enceladus lies under kilometers of ice, but some of its contents do reach the surface. Jets near the south pole spray out water vapor and icy particles, offering a way ...
This bird flies thousands of miles, but its wings have a catch
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How healthy are your feet?
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Berlin's High-End KaDeWe Store Opens Dedicated Health Hub
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Excitement mounts as new telescope nears first light
As the Fred Young Submillimeter Telescope nears first observations, Cornell scientists are preparing groundbreaking surveys of the early universe, galaxy formation and dark matter.
More on Radiacode 110
This is the second post reporting a few tests of the Radiacode 110 spectrometer, an extra-cool pocket dosimeter/radiation counter/spectrograph sold by RadiaCode.
Scientists Take Step Towards "Schrödinger’s Cat In Real Life" By Moving A One Centimeter Object Using A Quantum Effect
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DNA from centuries-old skeletons buried in Montreal reveals no genetic mixing between Indigenous people and French colonists
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Aged aircraft exhaust poses a rising threat to human health
Fine particulate matter consists of tiny particles with diameters in the nanometer range. They are produced, for example, by fuel combustion, remain suspended in the air and can penetrate deep into the respiratory tract.
Tiny platform creates and directs microbubbles on demand
Set within a 3-millimeter area on a chip, the new device produces hydrogen gas bubbles on a grid of electrodes, then powers the bubbles up with acoustic energy through ultrasound.
Daldrop Opens for Business in Southern Oswego County
$10 Million Facility in the L. Michael Treadwell Oswego County Industrial Park marks the largest expansion outside of Germany in the company’s 73-year history By Stefan Yablonski [caption id=attachment_11076 align=alignright width=450] Daldrop SBB CEO Jens Daldrop addresses attendees at the 2025 groundbreaking for the project. Daldrop also chairs the advisory board of Germany-based Daldrop Group.[/caption] A new era of cleanroom technology is underway in Central New York. The Daldrop Group’s advanced manufacturing facility and U.S. headquarters is physically built within the L. Michael Treadwell Oswego County Industrial Park. This industrial park is located in the town of Schroeppel. It marks the largest expansion outside of Germany in the company’s 73-year history. Daldrop SBB is based in Neckartailfingen, Germany. It is a global supplier of cleanroom technology, primarily to the pharmaceutical industry. It designs and builds advanced cleanroom environments for the pharmaceutical, biotechnology and medical technology industries. It nvested $10 million in the new project. “We broke ground in 2025; we were under construction all winter. We just opened this spring, early spring,” said Benjamin Morrow, operations manager and control. The company consolidated sites in Salina and DeWitt into the industrial park in Schroeppel, Morrow added. “The next move here is to maximize every square inch of this facility and then we are already looking at the expansion. So, it is more capital investment on equipment — definitely higher-end automation in additional equipment so we can produce more components and then to support the ever-growing base in North America,” Morrow continued. “We are the headquarters for service, maintenance and spare parts. So as Daldrop has more and more installations, they need more and more service, maintenance and spare parts. So that will come out of this facility as well — it already is.” “As a global leader in GMP (global manufacturing support) pharmaceutical cleanrooms for decades, I am very proud to bring manufacturing jobs to Upstate New York,” said Mike Sullivan, president of Daldrop US operations. Key to choosing Southern Oswego County [caption id=attachment_11077 align=alignright width=450] Daldrop SBB at the L. Michael Treadwell Oswego County Industrial Park when the company announced the start of construction.[/caption] Sullivan said that the selection of the Schroeppel industrial park was mainly due to the help of Operation Oswego County and two people in the organization. “Prior to being purchased by Daldrop International from the Stuttgart region of Germany, Vince Bongio was a founding partner in SBB Inc. as well as our head of engineering. We based out of Syracuse due to Vince’s skills in HVAC and the manufacturing capabilities found in Syracuse,” said Sullivan. Bongio moved to Syracuse from California in the 1970s to work in Carrier’s Industrial Division of Large-Scale Petrochemical Refrigeration. Next, he advanced to General Electric’s TV Tube Plant where he got into cleanrooms ,leading to his role of head of engineering for Clestra Cleanrooms where he met Sullivan, their New England distributor. “Vince Bongio is a phenomenal engineer. Formerly of Carrier, he grew up in California and went to Cal Poly,” Sullivan explained. “Carrier hired him right out of college and he moved to Syracuse. He is the reason we are in Syracuse today. He is retiring this year. We are very proud and his legacy is having brought Daldrop to Syracuse.” In 2000, Sullivan, Bazinet, Bongio Inc (SBB) was formed with engineering and manufacturing, based in Syracuse, and sales and construction based in Massachusetts as it is today. “SBB Inc. started in Syracuse. I had a design–build contracting firm out of Massachusetts that was primarily doing all the new technologies coming out of MIT,” Sullivan said. “I started a manufacturing side. A big thing for cleanrooms is the HVAC. Most cleanroom suppliers are architecturally focused people. The strength in Syracuse is HVAC. So, SBB developed with me running sales and construction out of Massachusetts and manufacturing out of Syracuse.” “Daldrop wanted to have a relationship in the States and of those who approached us, they were the only ones who really understood HVAC. So, we were the right fit for them. We did a joint venture focused out of Massachusetts from 2012 to 2018 leveraging their technologies,” Sullivan explained. “The commitment was if we brought their product to the States, we would do that if they built it here. “The pieces that had to be in place to make the investment, they wanted to acquire us, we were great with that. If you looked at business recommendations the general guidance was to build in a low labor area — something like North Carolina — but Syracuse had a strong background in HVAC and we chose Syracuse and Oswego County to be our headquarters in the States. So, it is built off of history, technology and the existing supply chain — bringing jobs back to the area.” During the initial discussions with Daldrop about coming to the U.S., SBB agreed to sell under the conditions Daldrop would manufacture in the U.S. There are many areas that offer incentives and economic packages, but the strength of HVAC expertise and skilled manufacturing was a big part of the discussions for site selection. Coming home [caption id=attachment_11078 align=alignright width=451] Construction moves forward in March at the L. Michael Treadwell Oswego County Industrial Park.[/caption] The second key person to building in Oswego County is Ben Morrow, Sullivan added. “Ben has been working with Daldrop SBB for more than 12 years and has advanced to COO of manufacturing and engineering. Ben grew up in Phoenix, so building a factory for the Germany company in Phoenix is a strong success for both his community and the appreciation of Ben’s skills as a team leader,” Sullivan said. “I went to high school in Phoenix. So, this is like full circle for me. It’s a small world,” Morrow said. “I hadn’t been back to Phoenix since graduation. This is one of the properties that John Trimble of C&S, he is the former president of C&S, he just retired, suggested. He and I were very good personal friends. John was from Mexico and I was from Phoenix. We knew each other from high school. And the architect of this building, Ed Smart of smartDESIGN Architecture in Batavia — I went to high school with him. So, this was a project that’s full circle a coming home kind of thing. The three of us knew each other — kind of like it was meant to be. Very serendipitous.” Schroeppel was one option for Daldrop to consider; the original intent was just to get a warehouse to store some product, he added. The facility is Daldrop’s largest outside of their native country. Total payroll at the facility will be approximately $2.4 million once fully staffed. “Here is 32,000 square feet and we plan to expand and put in an additional 10,000 square feet,” Morrow said. “We have 17.5 acres. We can put at least three more facilities here, just on this property. The master plan submitted for the current building is the first of possible three buildings on the campus.” “If we can find the right people and advance the production according to the plan, we should be able to grow for the next decade. One of the first jobs we filled was our new HR manager, with a primary focus posting and filling new positions,” Sullivan said. Stop the exodus, start hiring [caption id=attachment_11080 align=alignright width=452] Principals at the local Daldrop SBB headquarters, from left: Ben Morrow, Mike Sullivan and Jens Daldrop.[/caption] “I have been coming to Syracuse for 30 years. One of the things I had a hard time watching was the exodus of factories. One of the toughest things is to watch it with my partners’ kids who had to move away for jobs. It is important for us to give opportunity where people’s kids don’t have to leave the area to get work,” Sullivan said. “My responsibility is to find people who have skill sets that want to work and then I have to build opportunity for that work to happen. “After years of watching companies and Vince’s three sons all move out of the areas to get jobs, it is important to us to provide opportunities for the Syracuse region and help grow our company. We have been hiring for our new factory and will continue for the next few years.” “We are hiring and will continue to hire. Currently we have about 19 on staff right now,” Morrow said. “We expect to grow that by about 10 to 15 in the next 12 to 18 months or so. We are at 19 currently — one in the wings. It’s been great being able to hire locally. All these folks that we’ve been hiring, they all live within a few miles from here.” “We hired someone this past week (end of August). She grew up in the area, raised a family and is working down in Florida. She just took a job with us so she can move back and be with her family. We will be moving her back and she should be starting in October. We are very happy to see this happen,” Sullivan said. “I feel strongly about having a spot for the kids to not have to move out of the area. It is better to have people moving into the area.” Currently, Daldrop SBB has openings for finance manager, COO of construction and delivery, as well as mechanical, electrical designers and Revit modelers, construction managers, commissioning agents and many other skills that are needed. Along with Daldrop’s reputation in life science cleanrooms, there is a strong history in semiconductor, electronics, glass, photonics, aerospace and other markets. This may be helpful with any new technologies building in the market such as the Micron expansion and the support network, Sullivan said. “We acquired this property and closed on it two months before any announcement from Micron. It is serendipitous that they’re right down the street from us,” Morrow added. “Everybody started thinking ‘you guys are supporting Micron.’ We were here first. That is not a goal of ours. We may or may not … they are talking to us; it is an opportunity.” The long run [caption id=attachment_11079 align=alignright width=450] Benjamin Morrow, operations manager and control at Daldlrop, speaks during a recent ribbon-cutting event in Schroeppel.[/caption] “Long term, we will expand the Phoenix facility,” Sullivan said. “We built our facility with a campus approach. Sustainability is big. We designed our rooms to be more sustainable. Our building has no gas lines for heat. We put geothermal wells in the ground. We put heat pumps in for heating and cooling out of those wells and we put a large layer of solar panels up on the roof. We worked with National Grid for metering. Our building is a high efficiency model. We upgraded all the instillation and the glass filtering. So, it is a very green building. We will have a very minimal carbon footprint. It also adheres to LEED (Leadership in Energy and Environmental Design) construction standards.” “We are a bunch of HVAC engineers. We did a large scale geothermal and spent the money up front because we knew it made sense in the business sense in the environmental sense and sustainability,” Morrow said. “We have insulated metal panels on walls and roof; we are an envelope from the exterior.” Daldrop, as a global player, has a strong culture of sustainability that is found in all its products including the new facility. The building has been designed with (sixteen) 400-foot deep geothermal wells, high efficiency construction methods, approximately 70 kilowatt solar photovoltaic panels, electric vehicle chargers and 26% recycled content. “Daldrop thinks of long-term investing,” Sullivan said. “On the roof, photovoltaic panels supplement our power. Over half the energy that I use is coming from the sun. We have chargers up front for employee electric vehicles. This place is built to last. This slab that we are walking on, normal buildings are four inches, some go to six inches, we are nine inches all the way through — except where the heavy equipment is — that is 10 to 12 inches thick, solid concrete. It allows us to reconfigure for whatever type of equipment we want to bring in,” Morrow said. “We are authorized by Underwriters Laboratory to self-certify so we don’t need to have an inspector come out and recertify. We get audited often, but we certify our own electronics. The control system in this building is rather high-end. Our thermostat in every room is zoned, independent. We analyze the data; incorporate it with our solar panels.” “There is a lot of competition for people to work. It’s not just about how much salary they are going to make — it’s about the work environment, the ability for stability. We want to make sure our employees have the best environment to work in,” Morrow added. Similarities “One of the reasons I believe why Daldrop chose this area, Phoenix in particular, is because it is a village, a river-based village. Neckartailfingen in Germany where Daldrop is based is also a river-based village, manufacturing community. So, there is a lot of similarities — that smalltown feel,” Morrow said. “We have a lot of connections through multiple employees that lead back to Carrier, also. Everything came together, the timing everything.” “We are thankful for all the economic development support. Everyone has been helping make this happen. So, keep it up, it is working, that is all I got to say, Sullivan said. “If you look at historical industrial manufacturing, this region has skills that have been un-utilized. The northern industrial region has a lot of skills that if we can tap before they go away, we can leverage them. That is what we are trying to do. You’d be surprised at the supply chain left behind from Carrier — that supply chain is still there.” “Operation Oswego County has been fantastic,” Morrow added. “I can’t say enough good things about that group.” What Is Cleanroom Technology Cleanroom technology is a system of specialized engineering, filtration and operational controls used to maintain an extremely low concentration of airborne particles, microbes and chemical vapors. How It Works • Air Filtration: Uses HEPA or ULPA filters to remove 99.97% of tiny particles down to 0.3 microns. • Airflow Control: Directs air in a steady, unidirectional (laminar) or filtered turbulent pattern to push dust away from work areas. • Environmental Regulation: Maintains precise control over temperature, humidity and positive air pressure to block outside air leaks. • Specialized Attire: Requires personnel to wear full-body garments (“bunny suits”), gloves and masks to stop human shedding
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Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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